[llvm] [AArch64] Convert `CSEL(X, 1)` into `CSINC(X, XZR)` in early-ifcvt (PR #162993)

[Paul Walker via llvm-commits]

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@@ -976,6 +1000,14 @@ void AArch64InstrInfo::insertSelect(MachineBasicBlock &MBB,
 
     // Fold the operation. Leave any dead instructions for DCE to clean up.
     if (FoldedOpc) {
+      // NewVReg might be XZR/WZR. In that case create a COPY into a virtual
+      // register.
+      if (!Register::isVirtualRegister(NewVReg)) {
+        unsigned ZeroReg = NewVReg;
+        NewVReg = MRI.createVirtualRegister(RC);
+        BuildMI(MBB, I, DL, get(TargetOpcode::COPY), NewVReg).addReg(ZeroReg);
+      }
+
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paulwalker-arm wrote:

Do you know why this is necessary? I'm wondering if you can instead bypass things like `constrainRegClass` when NewVReg is not virtual, which might mean we'll never generate the copy (as seen in peephole_csel).

Perhaps add an assert that NewVReg is virtual or XZR/WZR to make it clearer why code is bypassed.

https://github.com/llvm/llvm-project/pull/162993