[llvm] [AMDGPU] Add regbankselect rules for G_ADD/SUB and variants (PR #159860)

[Anshil Gandhi via llvm-commits]

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@@ -470,7 +470,20 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
       .Uni(S16, {{Sgpr32Trunc}, {Sgpr32AExt, Sgpr32AExt}})
       .Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16}})
       .Uni(S32, {{Sgpr32}, {Sgpr32, Sgpr32}})
-      .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}});
+      .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}})
+      .Uni(V2S16, {{SgprV2S16}, {SgprV2S16, SgprV2S16}})
+      .Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}})
+      // Split 64-bit add/sub into two 32-bit ops on VGPRs
+      .Uni(S64, {{Sgpr64}, {Sgpr64, Sgpr64}, SplitTo32})
+      .Div(S64, {{Vgpr64}, {Vgpr64, Vgpr64}, SplitTo32});
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gandhi56 wrote:

Agreed for the SALU case.

I checked the ISA documentation for RDNA 4. There is no 64-bit addition on VALU. The current globalisel implementation and selectionDAG emit `v_add_co_u32` and `v_add_co_ci_u32_e64`

https://github.com/llvm/llvm-project/pull/159860