[llvm] [X86] Add baseline test for X86 conditional load/store optimization bug (PR #163354)

[via llvm-commits]

https://github.com/azwolski updated https://github.com/llvm/llvm-project/pull/163354

>From 00d3cb8466aef10b48b4cc8a3f88da5f262d4057 Mon Sep 17 00:00:00 2001
From: Antoni Zwolski <antoni.zwolski at intel.com>
Date: Tue, 14 Oct 2025 11:24:27 +0200
Subject: [PATCH 1/2] [X86] Add and_cond function with conditional logic for
 masked store

---
 llvm/test/CodeGen/X86/apx/cf.ll | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/CodeGen/X86/apx/cf.ll b/llvm/test/CodeGen/X86/apx/cf.ll
index b2651e91134ee..4cce2226a91fb 100644
--- a/llvm/test/CodeGen/X86/apx/cf.ll
+++ b/llvm/test/CodeGen/X86/apx/cf.ll
@@ -230,6 +230,24 @@ entry:
   ret void
 }
 
+define void @and_cond(i32 %a, i1 %b) {
+; CHECK-LABEL: and_cond:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    testl %edi, %edi
+; CHECK-NEXT:    setg %al
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    testb %al, %sil
+; CHECK-NEXT:    cfcmovel %ecx, 0
+; CHECK-NEXT:    retq
+entry:
+  %0 = icmp sgt i32 %a, 0
+  %1 = xor i1 %b, true
+  %3 = and i1 %1, %0
+  %4 = insertelement <1 x i1> zeroinitializer, i1 %3, i64 0
+  call void @llvm.masked.store.v1i32.p0(<1 x i32> zeroinitializer, ptr null, i32 1, <1 x i1> %4)
+  ret void
+}
+
 define i64 @redundant_test(i64 %num, ptr %p1, i64 %in) {
 ; CHECK-LABEL: redundant_test:
 ; CHECK:       # %bb.0:

>From 2f963468d0bb04b91856b70e302e77420c507124 Mon Sep 17 00:00:00 2001
From: Antoni Zwolski <antoni.zwolski at intel.com>
Date: Tue, 14 Oct 2025 23:32:56 +0200
Subject: [PATCH 2/2] [X86] Improve naming in and_cond test

---
 llvm/test/CodeGen/X86/apx/cf.ll | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/llvm/test/CodeGen/X86/apx/cf.ll b/llvm/test/CodeGen/X86/apx/cf.ll
index 4cce2226a91fb..af9d944428d3c 100644
--- a/llvm/test/CodeGen/X86/apx/cf.ll
+++ b/llvm/test/CodeGen/X86/apx/cf.ll
@@ -232,19 +232,18 @@ entry:
 
 define void @and_cond(i32 %a, i1 %b) {
 ; CHECK-LABEL: and_cond:
-; CHECK:       # %bb.0: # %entry
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    testl %edi, %edi
 ; CHECK-NEXT:    setg %al
 ; CHECK-NEXT:    xorl %ecx, %ecx
 ; CHECK-NEXT:    testb %al, %sil
 ; CHECK-NEXT:    cfcmovel %ecx, 0
 ; CHECK-NEXT:    retq
-entry:
-  %0 = icmp sgt i32 %a, 0
-  %1 = xor i1 %b, true
-  %3 = and i1 %1, %0
-  %4 = insertelement <1 x i1> zeroinitializer, i1 %3, i64 0
-  call void @llvm.masked.store.v1i32.p0(<1 x i32> zeroinitializer, ptr null, i32 1, <1 x i1> %4)
+  %is_pos = icmp sgt i32 %a, 0
+  %not_b = xor i1 %b, true
+  %cond = and i1 %not_b, %is_pos
+  %mask = insertelement <1 x i1> zeroinitializer, i1 %cond, i64 0
+  call void @llvm.masked.store.v1i32.p0(<1 x i32> zeroinitializer, ptr null, i32 1, <1 x i1> %mask)
   ret void
 }