[llvm] [DAGCombiner] Spill dynamic insertelt chain in one go (PR #162368)

[Princeton Ferro via llvm-commits]

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@@ -0,0 +1,358 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -O3 < %s -mcpu=sm_20 | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -mcpu=sm_20 | %ptxas-verify %}
+target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
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Prince781 wrote:

Changed.

https://github.com/llvm/llvm-project/pull/162368