[llvm] [RISCV][GISel] Fold `G_FCONSTANT` 0.0 store into `sw x0` (PR #163008)

[Matt Arsenault via llvm-commits]

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@@ -1049,6 +1049,19 @@ void RISCVInstructionSelector::preISelLower(MachineInstr &MI,
     MRI->setType(DstReg, sXLen);
     break;
   }
+  case TargetOpcode::G_STORE: {
+    Register SrcReg = MI.getOperand(0).getReg();
+    MachineInstr *Def = MRI->getVRegDef(SrcReg);
+    if (Def && Def->getOpcode() == TargetOpcode::G_FCONSTANT) {
+      if (Def->getOperand(1).getFPImm()->getValueAPF().isPosZero()) {
+        MI.getOperand(0).setReg(RISCV::X0);
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arsenm wrote:

AArch64 has a lot of weird hacking that I don't understand, but yes this should probably just be a combine 

https://github.com/llvm/llvm-project/pull/163008