[llvm] [RISCV][GISel] Fold `G_FCONSTANT` 0.0 store into `sw x0` (PR #163008)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,41 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -global-isel -mattr=+f -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=RV32
+; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=RV64
+
+define void @zero_f32(ptr %i) {
+; RV32-LABEL: zero_f32:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    sw zero, 0(a0)
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: zero_f32:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    sw zero, 0(a0)
+; RV64-NEXT:    ret
+entry:
+  store float 0.000000e+00, ptr %i, align 4
+  ret void
+}
+
+
+define void @zero_f64(ptr %i) {
+; RV32-LABEL: zero_f64:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    lui a1, %hi(.LCPI1_0)
+; RV32-NEXT:    addi a1, a1, %lo(.LCPI1_0)
+; RV32-NEXT:    lw a2, 0(a1)
+; RV32-NEXT:    lw a1, 4(a1)
+; RV32-NEXT:    sw a2, 0(a0)
+; RV32-NEXT:    sw a1, 4(a0)
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: zero_f64:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    sd zero, 0(a0)
+; RV64-NEXT:    ret
+entry:
+  store double 0.000000e+00, ptr %i, align 8
+  ret void
+}
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arsenm wrote:

test half and bfloat cases, and vectors? 

https://github.com/llvm/llvm-project/pull/163008