[llvm] [RISCV][GISel] Fold `G_FCONSTANT` 0.0 store into `sw x0` (PR #163008)

[Shaoce SUN via llvm-commits]

https://github.com/sunshaoce created https://github.com/llvm/llvm-project/pull/163008

None

>From 9225aa95ba8e05a60d1edd0b5e5310c5e7dc552b Mon Sep 17 00:00:00 2001
From: Shaoce SUN <sunshaoce at outlook.com>
Date: Sun, 12 Oct 2025 00:37:22 +0800
Subject: [PATCH 1/2] pre-commit

---
 .../RISCV/GlobalISel/store-fp-zero-to-x0.ll   | 44 +++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/store-fp-zero-to-x0.ll

diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/store-fp-zero-to-x0.ll b/llvm/test/CodeGen/RISCV/GlobalISel/store-fp-zero-to-x0.ll
new file mode 100644
index 0000000000000..4939fe11c5394
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/store-fp-zero-to-x0.ll
@@ -0,0 +1,44 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -global-isel -mattr=+f -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=RV32
+; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=RV64
+
+define void @zero_f32(ptr %i) {
+; RV32-LABEL: zero_f32:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    fmv.w.x fa5, zero
+; RV32-NEXT:    fsw fa5, 0(a0)
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: zero_f32:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    fmv.w.x fa5, zero
+; RV64-NEXT:    fsw fa5, 0(a0)
+; RV64-NEXT:    ret
+entry:
+  store float 0.000000e+00, ptr %i, align 4
+  ret void
+}
+
+
+define void @zero_f64(ptr %i) {
+; RV32-LABEL: zero_f64:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    lui a1, %hi(.LCPI1_0)
+; RV32-NEXT:    addi a1, a1, %lo(.LCPI1_0)
+; RV32-NEXT:    lw a2, 0(a1)
+; RV32-NEXT:    lw a1, 4(a1)
+; RV32-NEXT:    sw a2, 0(a0)
+; RV32-NEXT:    sw a1, 4(a0)
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: zero_f64:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    fmv.d.x fa5, zero
+; RV64-NEXT:    fsd fa5, 0(a0)
+; RV64-NEXT:    ret
+entry:
+  store double 0.000000e+00, ptr %i, align 8
+  ret void
+}

>From 9b25edd6384d722e1980fff61d51c0999d7b9d62 Mon Sep 17 00:00:00 2001
From: Shaoce SUN <sunshaoce at outlook.com>
Date: Sun, 12 Oct 2025 00:39:15 +0800
Subject: [PATCH 2/2] [RISCV][GISel] Fold `G_FCONSTANT` 0.0 store into `sw x0`

---
 .../Target/RISCV/GISel/RISCVInstructionSelector.cpp | 13 +++++++++++++
 .../CodeGen/RISCV/GlobalISel/store-fp-zero-to-x0.ll |  9 +++------
 2 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 53633eac3d2c3..54050242b1854 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -1049,6 +1049,19 @@ void RISCVInstructionSelector::preISelLower(MachineInstr &MI,
     MRI->setType(DstReg, sXLen);
     break;
   }
+  case TargetOpcode::G_STORE: {
+    Register SrcReg = MI.getOperand(0).getReg();
+    MachineInstr *Def = MRI->getVRegDef(SrcReg);
+    if (Def && Def->getOpcode() == TargetOpcode::G_FCONSTANT) {
+      if (Def->getOperand(1).getFPImm()->getValueAPF().isPosZero()) {
+        MI.getOperand(0).setReg(RISCV::X0);
+
+        if (MRI->use_nodbg_empty(SrcReg))
+          Def->eraseFromParent();
+      }
+    }
+    break;
+  }
   }
 }
 
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/store-fp-zero-to-x0.ll b/llvm/test/CodeGen/RISCV/GlobalISel/store-fp-zero-to-x0.ll
index 4939fe11c5394..d9a6e4b5ec53a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/store-fp-zero-to-x0.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/store-fp-zero-to-x0.ll
@@ -7,14 +7,12 @@
 define void @zero_f32(ptr %i) {
 ; RV32-LABEL: zero_f32:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    fmv.w.x fa5, zero
-; RV32-NEXT:    fsw fa5, 0(a0)
+; RV32-NEXT:    sw zero, 0(a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: zero_f32:
 ; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    fmv.w.x fa5, zero
-; RV64-NEXT:    fsw fa5, 0(a0)
+; RV64-NEXT:    sw zero, 0(a0)
 ; RV64-NEXT:    ret
 entry:
   store float 0.000000e+00, ptr %i, align 4
@@ -35,8 +33,7 @@ define void @zero_f64(ptr %i) {
 ;
 ; RV64-LABEL: zero_f64:
 ; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    fmv.d.x fa5, zero
-; RV64-NEXT:    fsd fa5, 0(a0)
+; RV64-NEXT:    sd zero, 0(a0)
 ; RV64-NEXT:    ret
 entry:
   store double 0.000000e+00, ptr %i, align 8