[llvm] [BranchRelaxation] Fix invalid branch generation in branch-relaxation (PR #162065)

[Sam Elliott via llvm-commits]

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@@ -491,6 +491,20 @@ bool BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) {
       return true;
     }
     if (FBB) {
+      // If we get here with a MBB which ends like this:
+      //
+      // bb.1:
+      // successors: %bb.2;
+      // ...
+      // BNE $x1, $x0, %bb.2
+      // PseudoBR %bb.2
+      //
+      // Just remove conditional branch.
+      if (TBB == FBB) {
+        BlockInfo[MBB->getNumber()].Size -= TII->getInstSizeInBytes(MI);
+        MI.eraseFromParent();
+        return true;
+      }
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lenary wrote:

For RISC-V, this seems correct.

I'm not entirely sure if we should be using a sequence of `removeBranch(MBB); insertUncondBranch(MBB, TBB)` instead of just removing one instruction, not being familiar with how all the targets define `removeBranch` and `insertUnconditionalBranch`. From the few I reviewed, they mostly do seem straightforward, but that's not guaranteed?

https://github.com/llvm/llvm-project/pull/162065