[llvm] [AMDGPU] Allow folding of non-subregs through REG_SEQUENCE (PR #151033)

[Josh Hutton via llvm-commits]

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@@ -1465,6 +1477,33 @@ void SIFoldOperandsImpl::foldOperand(
       return;
   }
 
+  if (!FoldingImmLike && OpToFold.isReg() && ST->needsAlignedVGPRs()) {
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JoshHuttonCode wrote:

Could you elaborate on your comment? Is your suggestion that I add an aligned 32-bit RC, and then use RegClassByHwMode to have the relevant DS_GWS instructions use that RC on the subtargets that require it? If we do not have a 32-bit aligned RC, I don't understand how this feature and padding during selection helps enforce the alignment at the time of folding.

https://github.com/llvm/llvm-project/pull/151033