[llvm] [AMDGPU][True16][CodeGen] si-fix-sgpr-copies legalize size mismatched V2S copy with subreg case (PR #161290)

[Brox Chen via llvm-commits]

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@@ -7565,6 +7570,65 @@ void SIInstrInfo::legalizeOperandsVALUt16(MachineInstr &MI,
     legalizeOperandsVALUt16(MI, OpIdx, MRI);
 }
 
+// Legalize operands of size-mismatches special inst between 16bit and 32bit
+// in moveToVALU lowering in true16 mode. This caused by 16bit
+// placed in both vgpr16 and sreg32 by isel. Including cases:
+// Copy
+// 1. dst32 = copy vgpr16 => dst32 = REG_SEQUENCE(vgpr16, lo16)
+// 2. dst32 = copy .lo16:vgpr32 / dst32 = copy .hi16:vgpr32
+//    => dst32 = REG_SEQUENCE(.lo16/hi16:vgpr32, lo16)
+// 3. sgpr16 = copy vgpr32/... (skipped, isel do not generate sgpr16)
+//
+// Reg_sequence
+// dst32 = reg_sequence(vgpr32, lo16/hi16)
+//    => dst32 = reg_sequence(.lo16:vgpr32, lo16/hi16)
+//
+// This can be removed after we have sgpr16 in place.
+void SIInstrInfo::legalizeSpecialInst_t16(MachineInstr &Inst,
+                                          MachineRegisterInfo &MRI) const {
+  unsigned Opcode = Inst.getOpcode();
+  const TargetRegisterClass *NewDstRC = getDestEquivalentVGPRClass(Inst);
+  switch (Opcode) {
+  case AMDGPU::COPY: {
+    Register SrcReg = Inst.getOperand(1).getReg();
+    if (!SrcReg.isVirtual() || !RI.isVGPR(MRI, SrcReg))
+      return;
+
+    bool SetSubReg = false;
+    Register SrcSubReg = Inst.getOperand(1).getSubReg();
+    const TargetRegisterClass *SrcRegRC = getOpRegClass(Inst, 1);
+    if (RI.getMatchingSuperRegClass(NewDstRC, SrcRegRC, AMDGPU::lo16)) {
+    } else if (NewDstRC == &AMDGPU::VGPR_32RegClass &&
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broxigarchen wrote:

This empty block is just to serve the return in the else branch

https://github.com/llvm/llvm-project/pull/161290