[llvm] [AArch64][NFC] Hoist TRI definition on AArch64InstrInfo::copyPhysReg (PR #162826)

[Tomer Shafir via llvm-commits]

https://github.com/tomershafir updated https://github.com/llvm/llvm-project/pull/162826

>From 3e34b7dc0aff7e3aa2194b37039343530f7489f0 Mon Sep 17 00:00:00 2001
From: tomershafir <tomer.shafir8 at gmail.com>
Date: Fri, 10 Oct 2025 15:10:29 +0300
Subject: [PATCH] [AArch64][NFC] Hoist TRI definition on
 AArch64InstrInfo::copyPhysReg

This patch hoists TRI definition on AArch64InstrInfo::copyPhysReg to remove code duplication and improve maintenance.

(From performance perspective, as its called for each copy instruction, it can reduce code size, register pressure seems unlikley, and modern processors should trigger this control flow anyway supporting ZCM/ZCZ.)

Also, change direct `RI` uses in that method to indirect `TRI` for consistent ecapsulation.
---
 llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 32 ++++++++------------
 1 file changed, 12 insertions(+), 20 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index cad9b1493b86b..c02a78fcaee7e 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -5066,10 +5066,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                    Register SrcReg, bool KillSrc,
                                    bool RenamableDest,
                                    bool RenamableSrc) const {
+  const TargetRegisterInfo *TRI = &getRegisterInfo();
+
   if (AArch64::GPR32spRegClass.contains(DestReg) &&
       (AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) {
-    const TargetRegisterInfo *TRI = &getRegisterInfo();
-
     if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) {
       // If either operand is WSP, expand to ADD #0.
       if (Subtarget.hasZeroCycleRegMoveGPR64() &&
@@ -5338,7 +5338,6 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
     if (Subtarget.hasZeroCycleRegMoveFPR128() &&
         !Subtarget.hasZeroCycleRegMoveFPR64() &&
         !Subtarget.hasZeroCycleRegMoveFPR32() && Subtarget.isNeonAvailable()) {
-      const TargetRegisterInfo *TRI = &getRegisterInfo();
       MCRegister DestRegQ = TRI->getMatchingSuperReg(DestReg, AArch64::dsub,
                                                      &AArch64::FPR128RegClass);
       MCRegister SrcRegQ = TRI->getMatchingSuperReg(SrcReg, AArch64::dsub,
@@ -5363,7 +5362,6 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
     if (Subtarget.hasZeroCycleRegMoveFPR128() &&
         !Subtarget.hasZeroCycleRegMoveFPR64() &&
         !Subtarget.hasZeroCycleRegMoveFPR32() && Subtarget.isNeonAvailable()) {
-      const TargetRegisterInfo *TRI = &getRegisterInfo();
       MCRegister DestRegQ = TRI->getMatchingSuperReg(DestReg, AArch64::ssub,
                                                      &AArch64::FPR128RegClass);
       MCRegister SrcRegQ = TRI->getMatchingSuperReg(SrcReg, AArch64::ssub,
@@ -5378,7 +5376,6 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
           .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
     } else if (Subtarget.hasZeroCycleRegMoveFPR64() &&
                !Subtarget.hasZeroCycleRegMoveFPR32()) {
-      const TargetRegisterInfo *TRI = &getRegisterInfo();
       MCRegister DestRegD = TRI->getMatchingSuperReg(DestReg, AArch64::ssub,
                                                      &AArch64::FPR64RegClass);
       MCRegister SrcRegD = TRI->getMatchingSuperReg(SrcReg, AArch64::ssub,
@@ -5402,7 +5399,6 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
     if (Subtarget.hasZeroCycleRegMoveFPR128() &&
         !Subtarget.hasZeroCycleRegMoveFPR64() &&
         !Subtarget.hasZeroCycleRegMoveFPR32() && Subtarget.isNeonAvailable()) {
-      const TargetRegisterInfo *TRI = &getRegisterInfo();
       MCRegister DestRegQ = TRI->getMatchingSuperReg(DestReg, AArch64::hsub,
                                                      &AArch64::FPR128RegClass);
       MCRegister SrcRegQ = TRI->getMatchingSuperReg(SrcReg, AArch64::hsub,
@@ -5417,7 +5413,6 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
           .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
     } else if (Subtarget.hasZeroCycleRegMoveFPR64() &&
                !Subtarget.hasZeroCycleRegMoveFPR32()) {
-      const TargetRegisterInfo *TRI = &getRegisterInfo();
       MCRegister DestRegD = TRI->getMatchingSuperReg(DestReg, AArch64::hsub,
                                                      &AArch64::FPR64RegClass);
       MCRegister SrcRegD = TRI->getMatchingSuperReg(SrcReg, AArch64::hsub,
@@ -5430,10 +5425,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
           .addReg(SrcRegD, RegState::Undef)
           .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
     } else {
-      DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
-                                       &AArch64::FPR32RegClass);
-      SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
-                                      &AArch64::FPR32RegClass);
+      DestReg = TRI->getMatchingSuperReg(DestReg, AArch64::hsub,
+                                         &AArch64::FPR32RegClass);
+      SrcReg = TRI->getMatchingSuperReg(SrcReg, AArch64::hsub,
+                                        &AArch64::FPR32RegClass);
       BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
           .addReg(SrcReg, getKillRegState(KillSrc));
     }
@@ -5445,7 +5440,6 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
     if (Subtarget.hasZeroCycleRegMoveFPR128() &&
         !Subtarget.hasZeroCycleRegMoveFPR64() &&
         !Subtarget.hasZeroCycleRegMoveFPR64() && Subtarget.isNeonAvailable()) {
-      const TargetRegisterInfo *TRI = &getRegisterInfo();
       MCRegister DestRegQ = TRI->getMatchingSuperReg(DestReg, AArch64::bsub,
                                                      &AArch64::FPR128RegClass);
       MCRegister SrcRegQ = TRI->getMatchingSuperReg(SrcReg, AArch64::bsub,
@@ -5460,7 +5454,6 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
           .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
     } else if (Subtarget.hasZeroCycleRegMoveFPR64() &&
                !Subtarget.hasZeroCycleRegMoveFPR32()) {
-      const TargetRegisterInfo *TRI = &getRegisterInfo();
       MCRegister DestRegD = TRI->getMatchingSuperReg(DestReg, AArch64::bsub,
                                                      &AArch64::FPR64RegClass);
       MCRegister SrcRegD = TRI->getMatchingSuperReg(SrcReg, AArch64::bsub,
@@ -5473,10 +5466,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
           .addReg(SrcRegD, RegState::Undef)
           .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
     } else {
-      DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
-                                       &AArch64::FPR32RegClass);
-      SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
-                                      &AArch64::FPR32RegClass);
+      DestReg = TRI->getMatchingSuperReg(DestReg, AArch64::bsub,
+                                         &AArch64::FPR32RegClass);
+      SrcReg = TRI->getMatchingSuperReg(SrcReg, AArch64::bsub,
+                                        &AArch64::FPR32RegClass);
       BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
           .addReg(SrcReg, getKillRegState(KillSrc));
     }
@@ -5536,9 +5529,8 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   }
 
 #ifndef NDEBUG
-  const TargetRegisterInfo &TRI = getRegisterInfo();
-  errs() << TRI.getRegAsmName(DestReg) << " = COPY "
-         << TRI.getRegAsmName(SrcReg) << "\n";
+  errs() << TRI->getRegAsmName(DestReg) << " = COPY "
+         << TRI->getRegAsmName(SrcReg) << "\n";
 #endif
   llvm_unreachable("unimplemented reg-to-reg copy");
 }