[clang] [llvm] [PowerPC][AIX] Specify correct ABI alignment for double (PR #144673)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 10 02:02:43 PDT 2025
https://github.com/nikic updated https://github.com/llvm/llvm-project/pull/144673
>From c69372599c7ddccad3db078d17a65d29b3666f95 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov at redhat.com>
Date: Wed, 11 Jun 2025 11:17:53 +0200
Subject: [PATCH 1/2] [PowerPC][AIX] Specify correct ABI alignment for double
Add `f64:32:64` to the data layout for AIX, to indicate that doubles
have a 32-bit ABI alignment and 64-bit preferred alignment.
Clang was already taking this into account, but it was not reflected
in LLVM's data layout.
Fixes https://github.com/llvm/llvm-project/issues/133599.
---
clang/lib/Basic/Targets/PPC.h | 4 +-
clang/lib/CodeGen/CodeGenModule.cpp | 14 +-
llvm/lib/IR/AutoUpgrade.cpp | 8 +-
llvm/lib/TargetParser/TargetDataLayout.cpp | 4 +
llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll | 152 +++++++--------
llvm/test/CodeGen/PowerPC/aix-cc-abi.ll | 174 ++++++++----------
.../PowerPC/aix-emit-tracebacktable.ll | 2 +-
llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll | 4 +-
.../CodeGen/PowerPC/aix32-cc-abi-vaarg-mir.ll | 59 +++---
.../CodeGen/PowerPC/aix32-cc-abi-vaarg.ll | 57 +++---
.../CodeGen/PowerPC/aix64-cc-abi-vaarg-mir.ll | 12 +-
.../CodeGen/PowerPC/aix64-cc-abi-vaarg.ll | 10 +-
.../Bitcode/DataLayoutUpgradeTest.cpp | 12 +-
13 files changed, 239 insertions(+), 273 deletions(-)
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 9f3a4cd2da716..b538ac64e7c42 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -390,7 +390,7 @@ class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
: PPCTargetInfo(Triple, Opts) {
if (Triple.isOSAIX())
- resetDataLayout("E-m:a-p:32:32-Fi32-i64:64-n32");
+ resetDataLayout("E-m:a-p:32:32-Fi32-i64:64-n32-f64:32:64");
else if (Triple.getArch() == llvm::Triple::ppcle)
resetDataLayout("e-m:e-p:32:32-Fn32-i64:64-n32");
else
@@ -449,7 +449,7 @@ class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
if (Triple.isOSAIX()) {
// TODO: Set appropriate ABI for AIX platform.
- DataLayout = "E-m:a-Fi64-i64:64-i128:128-n32:64";
+ DataLayout = "E-m:a-Fi64-i64:64-i128:128-n32:64-f64:32:64";
LongDoubleWidth = 64;
LongDoubleAlign = DoubleAlign = 32;
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp
index 8d019d4b2da25..e0782db6efd50 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -378,15 +378,11 @@ static void checkDataLayoutConsistency(const TargetInfo &Target,
Check("bfloat", llvm::Type::getBFloatTy(Context), Target.BFloat16Align);
Check("float", llvm::Type::getFloatingPointTy(Context, *Target.FloatFormat),
Target.FloatAlign);
- // FIXME: AIX specifies wrong double alignment in DataLayout
- if (!Triple.isOSAIX()) {
- Check("double",
- llvm::Type::getFloatingPointTy(Context, *Target.DoubleFormat),
- Target.DoubleAlign);
- Check("long double",
- llvm::Type::getFloatingPointTy(Context, *Target.LongDoubleFormat),
- Target.LongDoubleAlign);
- }
+ Check("double", llvm::Type::getFloatingPointTy(Context, *Target.DoubleFormat),
+ Target.DoubleAlign);
+ Check("long double",
+ llvm::Type::getFloatingPointTy(Context, *Target.LongDoubleFormat),
+ Target.LongDoubleAlign);
if (Target.hasFloat128Type())
Check("__float128", llvm::Type::getFP128Ty(Context), Target.Float128Align);
if (Target.hasIbm128Type())
diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp
index f28b98957cae4..b6d14a8a8d3b9 100644
--- a/llvm/lib/IR/AutoUpgrade.cpp
+++ b/llvm/lib/IR/AutoUpgrade.cpp
@@ -6120,7 +6120,13 @@ std::string llvm::UpgradeDataLayoutString(StringRef DL, StringRef TT) {
if (Pos != size_t(-1))
Res.insert(Pos + I64.size(), I128);
}
- return Res;
+ }
+
+ if (T.isPPC() && T.isOSAIX() && !DL.contains("f64:32:64") && !DL.empty()) {
+ size_t Pos = Res.find("-S128");
+ if (Pos == StringRef::npos)
+ Pos = Res.size();
+ Res.insert(Pos, "-f64:32:64");
}
if (!T.isX86())
diff --git a/llvm/lib/TargetParser/TargetDataLayout.cpp b/llvm/lib/TargetParser/TargetDataLayout.cpp
index cea246e9527bd..ca610b58afa67 100644
--- a/llvm/lib/TargetParser/TargetDataLayout.cpp
+++ b/llvm/lib/TargetParser/TargetDataLayout.cpp
@@ -246,6 +246,10 @@ static std::string computePowerDataLayout(const Triple &T) {
else
Ret += "-n32";
+ // The ABI alignment for doubles on AIX is 4 bytes.
+ if (T.isOSAIX())
+ Ret += "-f64:32:64";
+
// Specify the vector alignment explicitly. For v256i1 and v512i1, the
// calculated alignment would be 256*alignment(i1) and 512*alignment(i1),
// which is 256 and 512 bytes - way over aligned.
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
index 258ddf60088c1..02994811dc8af 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
@@ -636,7 +636,7 @@ define i32 @test_mix(float %f, i32 signext %i, double %d, i8 signext %c) {
; 32BIT-NEXT: renamable $f0 = nofpexcept FADDS killed renamable $f0, killed renamable $f1, implicit $rm
; 32BIT-NEXT: renamable $f0 = nofpexcept FCTIWZ killed renamable $f0, implicit $rm
; 32BIT-NEXT: STFD killed renamable $f0, 0, %stack.0 :: (store (s64) into %stack.0)
- ; 32BIT-NEXT: renamable $r3 = LWZ 4, %stack.0 :: (load (s32) from %stack.0 + 4, basealign 8)
+ ; 32BIT-NEXT: renamable $r3 = LWZ 4, %stack.0 :: (load (s32) from %stack.0 + 4)
; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3
;
; 64BIT-LABEL: name: test_mix
@@ -655,7 +655,7 @@ define i32 @test_mix(float %f, i32 signext %i, double %d, i8 signext %c) {
; 64BIT-NEXT: renamable $f0 = nofpexcept FADDS killed renamable $f0, killed renamable $f1, implicit $rm
; 64BIT-NEXT: renamable $f0 = nofpexcept FCTIWZ killed renamable $f0, implicit $rm
; 64BIT-NEXT: STFD killed renamable $f0, 0, %stack.0 :: (store (s64) into %stack.0)
- ; 64BIT-NEXT: renamable $x3 = LWZ8 4, %stack.0 :: (load (s32) from %stack.0 + 4, basealign 8)
+ ; 64BIT-NEXT: renamable $x3 = LWZ8 4, %stack.0 :: (load (s32) from %stack.0 + 4)
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
entry:
%conv = fpext float %f to double
@@ -956,11 +956,7 @@ define void @call_test_stackarg_float() {
; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r3 :: (dereferenceable load (s32) from @f)
; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r4 :: (dereferenceable load (s64) from @d)
; 32BIT-NEXT: ADJCALLSTACKDOWN 68, 0, implicit-def dead $r1, implicit $r1
- ; 32BIT-NEXT: STFD renamable $f2, 0, %stack.0 :: (store (s64) into %stack.0)
- ; 32BIT-NEXT: STFS renamable $f1, 56, $r1 :: (store (s32) into stack + 56, align 8, basealign 16)
- ; 32BIT-NEXT: renamable $r3 = LWZ 4, %stack.0 :: (load (s32) from %stack.0 + 4)
- ; 32BIT-NEXT: STW killed renamable $r3, 64, $r1 :: (store (s32) into stack + 64, align 16)
- ; 32BIT-NEXT: renamable $r11 = LWZ 0, %stack.0 :: (load (s32) from %stack.0, align 8)
+ ; 32BIT-NEXT: STFD renamable $f2, 60, $r1 :: (store (s64) into stack + 60, align 4, basealign 16)
; 32BIT-NEXT: $r3 = LI 1
; 32BIT-NEXT: $r4 = LI 2
; 32BIT-NEXT: $r5 = LI 3
@@ -969,8 +965,8 @@ define void @call_test_stackarg_float() {
; 32BIT-NEXT: $r8 = LI 6
; 32BIT-NEXT: $r9 = LI 7
; 32BIT-NEXT: $r10 = LI 8
- ; 32BIT-NEXT: STW killed renamable $r11, 60, $r1 :: (store (s32) into stack + 60, basealign 16)
- ; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $f1, implicit $f2, implicit $r2, implicit-def $r1
+ ; 32BIT-NEXT: STFS renamable $f1, 56, $r1 :: (store (s32) into stack + 56, align 8, basealign 16)
+ ; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $f1, implicit $f2, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 68, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
;
@@ -1057,11 +1053,7 @@ define void @call_test_stackarg_float3() {
; 32BIT-NEXT: renamable $r10 = LWZ 0, %stack.0 :: (load (s32) from %stack.0, align 8)
; 32BIT-NEXT: renamable $f2 = LFS 0, killed renamable $r3 :: (dereferenceable load (s32) from @f)
; 32BIT-NEXT: ADJCALLSTACKDOWN 64, 0, implicit-def dead $r1, implicit $r1
- ; 32BIT-NEXT: STFD renamable $f1, 0, %stack.1 :: (store (s64) into %stack.1)
; 32BIT-NEXT: STFS renamable $f2, 60, $r1 :: (store (s32) into stack + 60, basealign 16)
- ; 32BIT-NEXT: renamable $r3 = LWZ 4, %stack.1 :: (load (s32) from %stack.1 + 4)
- ; 32BIT-NEXT: STW killed renamable $r3, 56, $r1 :: (store (s32) into stack + 56, align 8, basealign 16)
- ; 32BIT-NEXT: renamable $r11 = LWZ 0, %stack.1 :: (load (s32) from %stack.1, align 8)
; 32BIT-NEXT: $r3 = LI 1
; 32BIT-NEXT: $r4 = LI 2
; 32BIT-NEXT: $r5 = LI 3
@@ -1069,8 +1061,8 @@ define void @call_test_stackarg_float3() {
; 32BIT-NEXT: $r7 = LI 5
; 32BIT-NEXT: $r8 = LI 6
; 32BIT-NEXT: $r9 = LI 7
- ; 32BIT-NEXT: STW killed renamable $r11, 52, $r1 :: (store (s32) into stack + 52, basealign 16)
- ; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float3[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $f1, implicit $r10, implicit $f2, implicit $r2, implicit-def $r1
+ ; 32BIT-NEXT: STFD renamable $f1, 52, $r1 :: (store (s64) into stack + 52, align 4, basealign 16)
+ ; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float3[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit $f1, implicit $r10, implicit $f2, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 64, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
;
@@ -1372,7 +1364,7 @@ define double @test_fpr_stack(double %d1, double %d2, double %d3, double %d4, do
; 32BIT: bb.0.entry:
; 32BIT-NEXT: liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13
; 32BIT-NEXT: {{ $}}
- ; 32BIT-NEXT: renamable $f0 = LFD 0, %fixed-stack.1 :: (load (s64) from %fixed-stack.1)
+ ; 32BIT-NEXT: renamable $f0 = LFD 0, %fixed-stack.1 :: (load (s64) from %fixed-stack.1, align 4)
; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm
; 32BIT-NEXT: renamable $f2 = LFS 0, %fixed-stack.2 :: (load (s32) from %fixed-stack.2, align 16)
; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f3, implicit $rm
@@ -1449,92 +1441,88 @@ define void @caller_fpr_stack() {
; 32BIT-NEXT: renamable $r3 = LWZtoc @d15, $r2 :: (load (s32) from got)
; 32BIT-NEXT: renamable $r4 = LWZtoc @f14, $r2 :: (load (s32) from got)
; 32BIT-NEXT: renamable $f0 = LFD 0, killed renamable $r3 :: (dereferenceable load (s64) from @d15)
- ; 32BIT-NEXT: renamable $r3 = LWZtoc @f16, $r2 :: (load (s32) from got)
- ; 32BIT-NEXT: renamable $r4 = LWZ 0, killed renamable $r4 :: (dereferenceable load (s32) from @f14)
- ; 32BIT-NEXT: renamable $r3 = LWZ 0, killed renamable $r3 :: (dereferenceable load (s32) from @f16)
+ ; 32BIT-NEXT: renamable $r5 = LWZtoc @f16, $r2 :: (load (s32) from got)
+ ; 32BIT-NEXT: renamable $r3 = LWZ 0, killed renamable $r4 :: (dereferenceable load (s32) from @f14)
+ ; 32BIT-NEXT: renamable $r4 = LWZ 0, killed renamable $r5 :: (dereferenceable load (s32) from @f16)
; 32BIT-NEXT: ADJCALLSTACKDOWN 144, 0, implicit-def dead $r1, implicit $r1
- ; 32BIT-NEXT: STFD killed renamable $f0, 0, %stack.0 :: (store (s64) into %stack.0)
; 32BIT-NEXT: renamable $r5 = LI 0
; 32BIT-NEXT: renamable $r6 = LIS 16352
- ; 32BIT-NEXT: STW killed renamable $r3, 140, $r1 :: (store (s32) into stack + 140, basealign 16)
- ; 32BIT-NEXT: renamable $r3 = LIS 13107
- ; 32BIT-NEXT: STW killed renamable $r4, 128, $r1 :: (store (s32) into stack + 128, align 16)
- ; 32BIT-NEXT: renamable $r4 = LIS 16355
; 32BIT-NEXT: STW killed renamable $r5, 60, $r1 :: (store (s32) into stack + 60, basealign 16)
- ; 32BIT-NEXT: renamable $r5 = LIS 26214
+ ; 32BIT-NEXT: renamable $r5 = LIS 13107
; 32BIT-NEXT: STW killed renamable $r6, 56, $r1 :: (store (s32) into stack + 56, align 8, basealign 16)
+ ; 32BIT-NEXT: renamable $r6 = LIS 16355
+ ; 32BIT-NEXT: renamable $r5 = ORI killed renamable $r5, 13107
+ ; 32BIT-NEXT: STW killed renamable $r5, 68, $r1 :: (store (s32) into stack + 68, basealign 16)
+ ; 32BIT-NEXT: renamable $r5 = LIS 26214
+ ; 32BIT-NEXT: renamable $r6 = ORI killed renamable $r6, 13107
+ ; 32BIT-NEXT: STW killed renamable $r6, 64, $r1 :: (store (s32) into stack + 64, align 16)
; 32BIT-NEXT: renamable $r6 = LIS 16358
- ; 32BIT-NEXT: renamable $r3 = ORI killed renamable $r3, 13107
- ; 32BIT-NEXT: STW killed renamable $r3, 68, $r1 :: (store (s32) into stack + 68, basealign 16)
- ; 32BIT-NEXT: renamable $r3 = LIS 39321
- ; 32BIT-NEXT: renamable $r4 = ORI killed renamable $r4, 13107
- ; 32BIT-NEXT: STW killed renamable $r4, 64, $r1 :: (store (s32) into stack + 64, align 16)
- ; 32BIT-NEXT: renamable $r4 = LIS 16361
; 32BIT-NEXT: renamable $r5 = ORI killed renamable $r5, 26214
; 32BIT-NEXT: STW killed renamable $r5, 76, $r1 :: (store (s32) into stack + 76, basealign 16)
- ; 32BIT-NEXT: renamable $r5 = LIS 52428
+ ; 32BIT-NEXT: renamable $r5 = LIS 39321
; 32BIT-NEXT: renamable $r6 = ORI killed renamable $r6, 26214
; 32BIT-NEXT: STW killed renamable $r6, 72, $r1 :: (store (s32) into stack + 72, align 8, basealign 16)
+ ; 32BIT-NEXT: renamable $r6 = LIS 16361
+ ; 32BIT-NEXT: renamable $r6 = ORI killed renamable $r6, 39321
+ ; 32BIT-NEXT: STW killed renamable $r6, 80, $r1 :: (store (s32) into stack + 80, align 16)
+ ; 32BIT-NEXT: renamable $r6 = LIS 52428
+ ; 32BIT-NEXT: renamable $r6 = ORI killed renamable $r6, 52429
+ ; 32BIT-NEXT: STW killed renamable $r6, 92, $r1 :: (store (s32) into stack + 92, basealign 16)
; 32BIT-NEXT: renamable $r6 = LIS 16364
- ; 32BIT-NEXT: renamable $r4 = ORI killed renamable $r4, 39321
- ; 32BIT-NEXT: STW killed renamable $r4, 80, $r1 :: (store (s32) into stack + 80, align 16)
- ; 32BIT-NEXT: renamable $r4 = LIS 16313
- ; 32BIT-NEXT: renamable $r5 = ORI killed renamable $r5, 52429
- ; 32BIT-NEXT: STW killed renamable $r5, 92, $r1 :: (store (s32) into stack + 92, basealign 16)
- ; 32BIT-NEXT: renamable $r5 = LIS 49807
- ; 32BIT-NEXT: renamable $r3 = ORI killed renamable $r3, 39322
- ; 32BIT-NEXT: STW renamable $r3, 84, $r1 :: (store (s32) into stack + 84, basealign 16)
+ ; 32BIT-NEXT: renamable $r5 = ORI killed renamable $r5, 39322
+ ; 32BIT-NEXT: STW renamable $r5, 84, $r1 :: (store (s32) into stack + 84, basealign 16)
; 32BIT-NEXT: renamable $r6 = ORI killed renamable $r6, 52428
; 32BIT-NEXT: STW killed renamable $r6, 88, $r1 :: (store (s32) into stack + 88, align 8, basealign 16)
+ ; 32BIT-NEXT: renamable $r6 = LIS 16313
+ ; 32BIT-NEXT: STW killed renamable $r5, 100, $r1 :: (store (s32) into stack + 100, basealign 16)
+ ; 32BIT-NEXT: renamable $r5 = LIS 49807
+ ; 32BIT-NEXT: renamable $r6 = ORI killed renamable $r6, 39321
+ ; 32BIT-NEXT: STW killed renamable $r6, 96, $r1 :: (store (s32) into stack + 96, align 16)
; 32BIT-NEXT: renamable $r6 = LIS 16316
- ; 32BIT-NEXT: STW killed renamable $r3, 100, $r1 :: (store (s32) into stack + 100, basealign 16)
- ; 32BIT-NEXT: renamable $r3 = LIS 60293
- ; 32BIT-NEXT: renamable $r4 = ORI killed renamable $r4, 39321
- ; 32BIT-NEXT: STW killed renamable $r4, 96, $r1 :: (store (s32) into stack + 96, align 16)
- ; 32BIT-NEXT: renamable $r4 = LIS 16318
; 32BIT-NEXT: renamable $r5 = ORI killed renamable $r5, 23593
; 32BIT-NEXT: STW killed renamable $r5, 108, $r1 :: (store (s32) into stack + 108, basealign 16)
- ; 32BIT-NEXT: renamable $r5 = LIS 2621
+ ; 32BIT-NEXT: renamable $r5 = LIS 60293
; 32BIT-NEXT: renamable $r6 = ORI killed renamable $r6, 10485
; 32BIT-NEXT: STW killed renamable $r6, 104, $r1 :: (store (s32) into stack + 104, align 8, basealign 16)
+ ; 32BIT-NEXT: renamable $r6 = LIS 16318
+ ; 32BIT-NEXT: renamable $r5 = ORI killed renamable $r5, 7864
+ ; 32BIT-NEXT: STW killed renamable $r5, 116, $r1 :: (store (s32) into stack + 116, basealign 16)
+ ; 32BIT-NEXT: renamable $r5 = LIS 2621
+ ; 32BIT-NEXT: renamable $r6 = ORI killed renamable $r6, 47185
+ ; 32BIT-NEXT: STW killed renamable $r6, 112, $r1 :: (store (s32) into stack + 112, align 16)
; 32BIT-NEXT: renamable $r6 = LIS 16320
- ; 32BIT-NEXT: renamable $r3 = ORI killed renamable $r3, 7864
- ; 32BIT-NEXT: STW killed renamable $r3, 116, $r1 :: (store (s32) into stack + 116, basealign 16)
- ; 32BIT-NEXT: renamable $r3 = LWZtoc %const.0, $r2 :: (load (s32) from got)
- ; 32BIT-NEXT: renamable $r4 = ORI killed renamable $r4, 47185
- ; 32BIT-NEXT: STW killed renamable $r4, 112, $r1 :: (store (s32) into stack + 112, align 16)
- ; 32BIT-NEXT: renamable $r4 = ORI killed renamable $r5, 28836
- ; 32BIT-NEXT: STW killed renamable $r4, 124, $r1 :: (store (s32) into stack + 124, basealign 16)
- ; 32BIT-NEXT: renamable $r4 = ORI killed renamable $r6, 41943
- ; 32BIT-NEXT: STW killed renamable $r4, 120, $r1 :: (store (s32) into stack + 120, align 8, basealign 16)
- ; 32BIT-NEXT: renamable $r4 = LWZtoc %const.1, $r2 :: (load (s32) from got)
- ; 32BIT-NEXT: renamable $r5 = LWZ 4, %stack.0 :: (load (s32) from %stack.0 + 4)
- ; 32BIT-NEXT: renamable $r6 = LWZtoc %const.2, $r2 :: (load (s32) from got)
- ; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r3 :: (load (s64) from constant-pool)
- ; 32BIT-NEXT: renamable $r3 = LWZtoc %const.3, $r2 :: (load (s32) from got)
- ; 32BIT-NEXT: renamable $f3 = LFD 0, killed renamable $r4 :: (load (s64) from constant-pool)
- ; 32BIT-NEXT: renamable $r4 = LWZtoc %const.4, $r2 :: (load (s32) from got)
- ; 32BIT-NEXT: renamable $f4 = LFD 0, killed renamable $r6 :: (load (s64) from constant-pool)
+ ; 32BIT-NEXT: renamable $r5 = ORI killed renamable $r5, 28836
+ ; 32BIT-NEXT: STW killed renamable $r5, 124, $r1 :: (store (s32) into stack + 124, basealign 16)
+ ; 32BIT-NEXT: renamable $r5 = LWZtoc %const.0, $r2 :: (load (s32) from got)
+ ; 32BIT-NEXT: renamable $r6 = ORI killed renamable $r6, 41943
+ ; 32BIT-NEXT: STW killed renamable $r6, 120, $r1 :: (store (s32) into stack + 120, align 8, basealign 16)
+ ; 32BIT-NEXT: renamable $r6 = LWZtoc %const.1, $r2 :: (load (s32) from got)
+ ; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r5 :: (load (s64) from constant-pool)
+ ; 32BIT-NEXT: renamable $r5 = LWZtoc %const.2, $r2 :: (load (s32) from got)
+ ; 32BIT-NEXT: renamable $f3 = LFD 0, killed renamable $r6 :: (load (s64) from constant-pool)
+ ; 32BIT-NEXT: renamable $r6 = LWZtoc %const.3, $r2 :: (load (s32) from got)
+ ; 32BIT-NEXT: renamable $f4 = LFD 0, killed renamable $r5 :: (load (s64) from constant-pool)
+ ; 32BIT-NEXT: renamable $r5 = LWZtoc %const.4, $r2 :: (load (s32) from got)
+ ; 32BIT-NEXT: renamable $f6 = LFD 0, killed renamable $r6 :: (load (s64) from constant-pool)
; 32BIT-NEXT: renamable $r6 = LWZtoc %const.5, $r2 :: (load (s32) from got)
- ; 32BIT-NEXT: renamable $f6 = LFD 0, killed renamable $r3 :: (load (s64) from constant-pool)
- ; 32BIT-NEXT: renamable $r3 = LWZtoc %const.6, $r2 :: (load (s32) from got)
- ; 32BIT-NEXT: renamable $f7 = LFD 0, killed renamable $r4 :: (load (s64) from constant-pool)
- ; 32BIT-NEXT: renamable $r4 = LWZtoc %const.7, $r2 :: (load (s32) from got)
+ ; 32BIT-NEXT: renamable $f7 = LFD 0, killed renamable $r5 :: (load (s64) from constant-pool)
+ ; 32BIT-NEXT: renamable $r5 = LWZtoc %const.6, $r2 :: (load (s32) from got)
; 32BIT-NEXT: renamable $f8 = LFD 0, killed renamable $r6 :: (load (s64) from constant-pool)
- ; 32BIT-NEXT: renamable $r6 = LWZtoc %const.8, $r2 :: (load (s32) from got)
- ; 32BIT-NEXT: renamable $f9 = LFD 0, killed renamable $r3 :: (load (s64) from constant-pool)
- ; 32BIT-NEXT: renamable $r3 = LWZtoc %const.9, $r2 :: (load (s32) from got)
- ; 32BIT-NEXT: renamable $f1 = LFD 0, killed renamable $r4 :: (load (s64) from constant-pool)
- ; 32BIT-NEXT: renamable $r4 = LWZtoc %const.10, $r2 :: (load (s32) from got)
- ; 32BIT-NEXT: renamable $f11 = LFD 0, killed renamable $r6 :: (load (s64) from constant-pool)
+ ; 32BIT-NEXT: renamable $r6 = LWZtoc %const.7, $r2 :: (load (s32) from got)
+ ; 32BIT-NEXT: renamable $f9 = LFD 0, killed renamable $r5 :: (load (s64) from constant-pool)
+ ; 32BIT-NEXT: renamable $r5 = LWZtoc %const.8, $r2 :: (load (s32) from got)
+ ; 32BIT-NEXT: renamable $f1 = LFD 0, killed renamable $r6 :: (load (s64) from constant-pool)
+ ; 32BIT-NEXT: renamable $r6 = LWZtoc %const.9, $r2 :: (load (s32) from got)
+ ; 32BIT-NEXT: renamable $f11 = LFD 0, killed renamable $r5 :: (load (s64) from constant-pool)
+ ; 32BIT-NEXT: renamable $r5 = LWZtoc %const.10, $r2 :: (load (s32) from got)
+ ; 32BIT-NEXT: renamable $f12 = LFD 0, killed renamable $r6 :: (load (s64) from constant-pool)
; 32BIT-NEXT: renamable $r6 = LWZtoc %const.11, $r2 :: (load (s32) from got)
- ; 32BIT-NEXT: renamable $f12 = LFD 0, killed renamable $r3 :: (load (s64) from constant-pool)
- ; 32BIT-NEXT: renamable $f13 = LFD 0, killed renamable $r4 :: (load (s64) from constant-pool)
+ ; 32BIT-NEXT: renamable $f13 = LFD 0, killed renamable $r5 :: (load (s64) from constant-pool)
; 32BIT-NEXT: renamable $f5 = LFS 0, killed renamable $r6 :: (load (s32) from constant-pool)
- ; 32BIT-NEXT: STW killed renamable $r5, 136, $r1 :: (store (s32) into stack + 136, align 8, basealign 16)
- ; 32BIT-NEXT: renamable $r3 = LWZ 0, %stack.0 :: (load (s32) from %stack.0, align 8)
+ ; 32BIT-NEXT: STW killed renamable $r4, 140, $r1 :: (store (s32) into stack + 140, basealign 16)
+ ; 32BIT-NEXT: STFD killed renamable $f0, 132, $r1 :: (store (s64) into stack + 132, align 4, basealign 16)
; 32BIT-NEXT: $f10 = COPY renamable $f1
- ; 32BIT-NEXT: STW killed renamable $r3, 132, $r1 :: (store (s32) into stack + 132, basealign 16)
+ ; 32BIT-NEXT: STW killed renamable $r3, 128, $r1 :: (store (s32) into stack + 128, align 16)
; 32BIT-NEXT: BL_NOP <mcsymbol .test_fpr_stack>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit killed $f10, implicit $f11, implicit $f12, implicit $f13, implicit $r2, implicit-def $r1, implicit-def dead $f1
; 32BIT-NEXT: ADJCALLSTACKUP 144, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
@@ -1647,7 +1635,7 @@ define i32 @mix_callee(double %d1, double %d2, double %d3, double %d4, i8 zeroex
; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
; 32BIT-NEXT: renamable $f0 = nofpexcept FCTIWZ killed renamable $f0, implicit $rm
; 32BIT-NEXT: STFD killed renamable $f0, 0, %stack.0 :: (store (s64) into %stack.0)
- ; 32BIT-NEXT: renamable $r3 = LWZ 4, %stack.0 :: (load (s32) from %stack.0 + 4, basealign 8)
+ ; 32BIT-NEXT: renamable $r3 = LWZ 4, %stack.0 :: (load (s32) from %stack.0 + 4)
; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3
;
; 64BIT-LABEL: name: mix_callee
@@ -1671,7 +1659,7 @@ define i32 @mix_callee(double %d1, double %d2, double %d3, double %d4, i8 zeroex
; 64BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
; 64BIT-NEXT: renamable $f0 = nofpexcept FCTIWZ killed renamable $f0, implicit $rm
; 64BIT-NEXT: STFD killed renamable $f0, 0, %stack.0 :: (store (s64) into %stack.0)
- ; 64BIT-NEXT: renamable $x3 = LWZ8 4, %stack.0 :: (load (s32) from %stack.0 + 4, basealign 8)
+ ; 64BIT-NEXT: renamable $x3 = LWZ8 4, %stack.0 :: (load (s32) from %stack.0 + 4)
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
entry:
%add = fadd double %d1, %d2
@@ -1791,7 +1779,7 @@ define void @caller_mix() {
; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f30, implicit $rm
; 32BIT-NEXT: renamable $f0 = nofpexcept FCTIWZ killed renamable $f0, implicit $rm
; 32BIT-NEXT: STFD killed renamable $f0, 0, %stack.0 :: (store (s64) into %stack.0)
- ; 32BIT-NEXT: renamable $r3 = LWZ 4, %stack.0 :: (load (s32) from %stack.0 + 4, basealign 8)
+ ; 32BIT-NEXT: renamable $r3 = LWZ 4, %stack.0 :: (load (s32) from %stack.0 + 4)
; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3
;
; 64BIT-LABEL: name: mix_floats
@@ -1826,7 +1814,7 @@ define void @caller_mix() {
; 64BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f1, killed renamable $f0, implicit $rm
; 64BIT-NEXT: renamable $f0 = nofpexcept FCTIWZ killed renamable $f0, implicit $rm
; 64BIT-NEXT: STFD killed renamable $f0, 0, %stack.0 :: (store (s64) into %stack.0)
- ; 64BIT-NEXT: renamable $x3 = LWZ8 4, %stack.0 :: (load (s32) from %stack.0 + 4, basealign 8)
+ ; 64BIT-NEXT: renamable $x3 = LWZ8 4, %stack.0 :: (load (s32) from %stack.0 + 4)
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
entry:
%add = add nsw i32 %i1, %i2
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
index 03770d22d9f4f..5ed0dfb258f73 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
@@ -1012,22 +1012,18 @@ define void @call_test_stackarg_float() {
; ASM32PWR4-NEXT: lwz 3, L..C8(2) # @f
; ASM32PWR4-NEXT: stw 0, 88(1)
; ASM32PWR4-NEXT: li 4, 2
+; ASM32PWR4-NEXT: li 5, 3
; ASM32PWR4-NEXT: li 6, 4
; ASM32PWR4-NEXT: li 7, 5
-; ASM32PWR4-NEXT: li 8, 6
; ASM32PWR4-NEXT: lfs 1, 0(3)
; ASM32PWR4-NEXT: lwz 3, L..C9(2) # @d
+; ASM32PWR4-NEXT: li 8, 6
; ASM32PWR4-NEXT: li 9, 7
-; ASM32PWR4-NEXT: li 10, 8
; ASM32PWR4-NEXT: lfd 2, 0(3)
; ASM32PWR4-NEXT: li 3, 1
-; ASM32PWR4-NEXT: stfd 2, 72(1)
-; ASM32PWR4-NEXT: lwz 5, 76(1)
-; ASM32PWR4-NEXT: lwz 11, 72(1)
-; ASM32PWR4-NEXT: stw 5, 64(1)
-; ASM32PWR4-NEXT: li 5, 3
+; ASM32PWR4-NEXT: li 10, 8
+; ASM32PWR4-NEXT: stfd 2, 60(1)
; ASM32PWR4-NEXT: stfs 1, 56(1)
-; ASM32PWR4-NEXT: stw 11, 60(1)
; ASM32PWR4-NEXT: bl .test_stackarg_float[PR]
; ASM32PWR4-NEXT: nop
; ASM32PWR4-NEXT: addi 1, 1, 80
@@ -1130,24 +1126,20 @@ define void @call_test_stackarg_float3() {
; ASM32PWR4-NEXT: stwu 1, -80(1)
; ASM32PWR4-NEXT: lwz 3, L..C9(2) # @d
; ASM32PWR4-NEXT: stw 0, 88(1)
+; ASM32PWR4-NEXT: li 4, 2
; ASM32PWR4-NEXT: li 5, 3
; ASM32PWR4-NEXT: li 6, 4
; ASM32PWR4-NEXT: li 7, 5
-; ASM32PWR4-NEXT: li 8, 6
; ASM32PWR4-NEXT: lfd 1, 0(3)
; ASM32PWR4-NEXT: lwz 3, L..C8(2) # @f
+; ASM32PWR4-NEXT: li 8, 6
; ASM32PWR4-NEXT: li 9, 7
; ASM32PWR4-NEXT: stfd 1, 72(1)
+; ASM32PWR4-NEXT: lwz 10, 72(1)
; ASM32PWR4-NEXT: lfs 2, 0(3)
; ASM32PWR4-NEXT: li 3, 1
-; ASM32PWR4-NEXT: stfd 1, 64(1)
-; ASM32PWR4-NEXT: lwz 4, 68(1)
-; ASM32PWR4-NEXT: lwz 10, 72(1)
-; ASM32PWR4-NEXT: lwz 11, 64(1)
-; ASM32PWR4-NEXT: stw 4, 56(1)
-; ASM32PWR4-NEXT: li 4, 2
; ASM32PWR4-NEXT: stfs 2, 60(1)
-; ASM32PWR4-NEXT: stw 11, 52(1)
+; ASM32PWR4-NEXT: stfd 1, 52(1)
; ASM32PWR4-NEXT: bl .test_stackarg_float3[PR]
; ASM32PWR4-NEXT: nop
; ASM32PWR4-NEXT: addi 1, 1, 80
@@ -1570,99 +1562,95 @@ define void @caller_fpr_stack() {
; ASM32PWR4-LABEL: caller_fpr_stack:
; ASM32PWR4: # %bb.0: # %entry
; ASM32PWR4-NEXT: mflr 0
-; ASM32PWR4-NEXT: stwu 1, -160(1)
+; ASM32PWR4-NEXT: stwu 1, -144(1)
; ASM32PWR4-NEXT: lwz 3, L..C19(2) # @d15
-; ASM32PWR4-NEXT: stw 0, 168(1)
-; ASM32PWR4-NEXT: lwz 5, L..C20(2) # %const.1
-; ASM32PWR4-NEXT: lwz 4, L..C21(2) # @f14
+; ASM32PWR4-NEXT: lwz 4, L..C20(2) # @f14
+; ASM32PWR4-NEXT: lwz 5, L..C21(2) # @f16
+; ASM32PWR4-NEXT: stw 0, 152(1)
+; ASM32PWR4-NEXT: lis 6, 16361
+; ASM32PWR4-NEXT: ori 6, 6, 39321
; ASM32PWR4-NEXT: lfd 0, 0(3)
-; ASM32PWR4-NEXT: lwz 3, L..C22(2) # @f16
-; ASM32PWR4-NEXT: lwz 3, 0(3)
-; ASM32PWR4-NEXT: stw 3, 140(1)
-; ASM32PWR4-NEXT: li 3, 0
-; ASM32PWR4-NEXT: stw 3, 60(1)
-; ASM32PWR4-NEXT: lis 3, 16352
-; ASM32PWR4-NEXT: stw 3, 56(1)
-; ASM32PWR4-NEXT: lis 3, 13107
-; ASM32PWR4-NEXT: ori 3, 3, 13107
-; ASM32PWR4-NEXT: stw 3, 68(1)
-; ASM32PWR4-NEXT: lis 3, 16355
-; ASM32PWR4-NEXT: ori 3, 3, 13107
-; ASM32PWR4-NEXT: stw 3, 64(1)
-; ASM32PWR4-NEXT: lis 3, 26214
-; ASM32PWR4-NEXT: ori 3, 3, 26214
-; ASM32PWR4-NEXT: stw 3, 76(1)
-; ASM32PWR4-NEXT: lis 3, 16358
-; ASM32PWR4-NEXT: ori 3, 3, 26214
-; ASM32PWR4-NEXT: stw 3, 72(1)
-; ASM32PWR4-NEXT: lis 3, -26215
-; ASM32PWR4-NEXT: ori 3, 3, 39322
-; ASM32PWR4-NEXT: stw 3, 84(1)
-; ASM32PWR4-NEXT: stw 3, 100(1)
-; ASM32PWR4-NEXT: lis 3, 16313
-; ASM32PWR4-NEXT: ori 3, 3, 39321
-; ASM32PWR4-NEXT: stw 3, 96(1)
-; ASM32PWR4-NEXT: lis 3, -15729
-; ASM32PWR4-NEXT: ori 3, 3, 23593
-; ASM32PWR4-NEXT: stw 3, 108(1)
-; ASM32PWR4-NEXT: lis 3, 16316
-; ASM32PWR4-NEXT: ori 3, 3, 10485
-; ASM32PWR4-NEXT: stw 3, 104(1)
-; ASM32PWR4-NEXT: lis 3, -5243
-; ASM32PWR4-NEXT: ori 3, 3, 7864
-; ASM32PWR4-NEXT: stw 3, 116(1)
-; ASM32PWR4-NEXT: lis 3, 16318
-; ASM32PWR4-NEXT: ori 3, 3, 47185
-; ASM32PWR4-NEXT: stw 3, 112(1)
-; ASM32PWR4-NEXT: lis 3, 2621
-; ASM32PWR4-NEXT: ori 3, 3, 28836
-; ASM32PWR4-NEXT: stw 3, 124(1)
-; ASM32PWR4-NEXT: lis 3, 16320
-; ASM32PWR4-NEXT: ori 3, 3, 41943
-; ASM32PWR4-NEXT: stw 3, 120(1)
-; ASM32PWR4-NEXT: lwz 3, L..C23(2) # %const.0
-; ASM32PWR4-NEXT: lfd 2, 0(3)
-; ASM32PWR4-NEXT: lwz 3, L..C24(2) # %const.2
+; ASM32PWR4-NEXT: lwz 3, 0(4)
+; ASM32PWR4-NEXT: lwz 4, 0(5)
+; ASM32PWR4-NEXT: li 5, 0
+; ASM32PWR4-NEXT: stw 5, 60(1)
+; ASM32PWR4-NEXT: lis 5, 16352
+; ASM32PWR4-NEXT: stw 5, 56(1)
+; ASM32PWR4-NEXT: lis 5, 13107
+; ASM32PWR4-NEXT: ori 5, 5, 13107
+; ASM32PWR4-NEXT: stw 5, 68(1)
+; ASM32PWR4-NEXT: lis 5, 16355
+; ASM32PWR4-NEXT: ori 5, 5, 13107
+; ASM32PWR4-NEXT: stw 5, 64(1)
+; ASM32PWR4-NEXT: lis 5, 26214
+; ASM32PWR4-NEXT: ori 5, 5, 26214
+; ASM32PWR4-NEXT: stw 5, 76(1)
+; ASM32PWR4-NEXT: lis 5, 16358
+; ASM32PWR4-NEXT: ori 5, 5, 26214
+; ASM32PWR4-NEXT: stw 5, 72(1)
+; ASM32PWR4-NEXT: lis 5, -26215
+; ASM32PWR4-NEXT: ori 5, 5, 39322
+; ASM32PWR4-NEXT: stw 5, 84(1)
+; ASM32PWR4-NEXT: stw 5, 100(1)
+; ASM32PWR4-NEXT: lis 5, 16313
+; ASM32PWR4-NEXT: ori 5, 5, 39321
+; ASM32PWR4-NEXT: stw 5, 96(1)
+; ASM32PWR4-NEXT: lis 5, -15729
+; ASM32PWR4-NEXT: ori 5, 5, 23593
+; ASM32PWR4-NEXT: stw 5, 108(1)
+; ASM32PWR4-NEXT: lis 5, 16316
+; ASM32PWR4-NEXT: ori 5, 5, 10485
+; ASM32PWR4-NEXT: stw 5, 104(1)
+; ASM32PWR4-NEXT: lis 5, -5243
+; ASM32PWR4-NEXT: ori 5, 5, 7864
+; ASM32PWR4-NEXT: stw 5, 116(1)
+; ASM32PWR4-NEXT: lis 5, 16318
+; ASM32PWR4-NEXT: ori 5, 5, 47185
+; ASM32PWR4-NEXT: stw 6, 80(1)
+; ASM32PWR4-NEXT: lis 6, -13108
+; ASM32PWR4-NEXT: ori 6, 6, 52429
+; ASM32PWR4-NEXT: stw 5, 112(1)
+; ASM32PWR4-NEXT: lis 5, 2621
+; ASM32PWR4-NEXT: ori 5, 5, 28836
+; ASM32PWR4-NEXT: stw 6, 92(1)
+; ASM32PWR4-NEXT: lis 6, 16364
+; ASM32PWR4-NEXT: ori 6, 6, 52428
+; ASM32PWR4-NEXT: stw 5, 124(1)
+; ASM32PWR4-NEXT: lis 5, 16320
+; ASM32PWR4-NEXT: ori 5, 5, 41943
+; ASM32PWR4-NEXT: stw 6, 88(1)
+; ASM32PWR4-NEXT: lwz 6, L..C22(2) # %const.0
+; ASM32PWR4-NEXT: stw 5, 120(1)
+; ASM32PWR4-NEXT: lwz 5, L..C23(2) # %const.1
+; ASM32PWR4-NEXT: lfd 2, 0(6)
+; ASM32PWR4-NEXT: lwz 6, L..C24(2) # %const.2
; ASM32PWR4-NEXT: lfd 3, 0(5)
; ASM32PWR4-NEXT: lwz 5, L..C25(2) # %const.3
-; ASM32PWR4-NEXT: lfd 4, 0(3)
-; ASM32PWR4-NEXT: lwz 3, L..C26(2) # %const.4
+; ASM32PWR4-NEXT: lfd 4, 0(6)
+; ASM32PWR4-NEXT: lwz 6, L..C26(2) # %const.4
; ASM32PWR4-NEXT: lfd 6, 0(5)
; ASM32PWR4-NEXT: lwz 5, L..C27(2) # %const.5
-; ASM32PWR4-NEXT: lwz 4, 0(4)
-; ASM32PWR4-NEXT: lfd 7, 0(3)
-; ASM32PWR4-NEXT: lwz 3, L..C28(2) # %const.6
+; ASM32PWR4-NEXT: lfd 7, 0(6)
+; ASM32PWR4-NEXT: lwz 6, L..C28(2) # %const.6
; ASM32PWR4-NEXT: lfd 8, 0(5)
; ASM32PWR4-NEXT: lwz 5, L..C29(2) # %const.7
-; ASM32PWR4-NEXT: stw 4, 128(1)
-; ASM32PWR4-NEXT: lis 4, 16361
-; ASM32PWR4-NEXT: ori 4, 4, 39321
-; ASM32PWR4-NEXT: lfd 9, 0(3)
-; ASM32PWR4-NEXT: lwz 3, L..C30(2) # %const.8
+; ASM32PWR4-NEXT: lfd 9, 0(6)
+; ASM32PWR4-NEXT: lwz 6, L..C30(2) # %const.8
; ASM32PWR4-NEXT: lfd 1, 0(5)
; ASM32PWR4-NEXT: lwz 5, L..C31(2) # %const.9
-; ASM32PWR4-NEXT: stw 4, 80(1)
-; ASM32PWR4-NEXT: lis 4, -13108
+; ASM32PWR4-NEXT: lfd 11, 0(6)
+; ASM32PWR4-NEXT: lwz 6, L..C32(2) # %const.10
; ASM32PWR4-NEXT: fmr 10, 1
-; ASM32PWR4-NEXT: ori 4, 4, 52429
-; ASM32PWR4-NEXT: lfd 11, 0(3)
-; ASM32PWR4-NEXT: lwz 3, L..C32(2) # %const.10
; ASM32PWR4-NEXT: lfd 12, 0(5)
; ASM32PWR4-NEXT: lwz 5, L..C33(2) # %const.11
-; ASM32PWR4-NEXT: stw 4, 92(1)
-; ASM32PWR4-NEXT: lis 4, 16364
-; ASM32PWR4-NEXT: ori 4, 4, 52428
-; ASM32PWR4-NEXT: stfd 0, 152(1)
-; ASM32PWR4-NEXT: stw 4, 88(1)
-; ASM32PWR4-NEXT: lwz 4, 156(1)
-; ASM32PWR4-NEXT: lfd 13, 0(3)
+; ASM32PWR4-NEXT: lfd 13, 0(6)
; ASM32PWR4-NEXT: lfs 5, 0(5)
-; ASM32PWR4-NEXT: lwz 3, 152(1)
-; ASM32PWR4-NEXT: stw 4, 136(1)
-; ASM32PWR4-NEXT: stw 3, 132(1)
+; ASM32PWR4-NEXT: stfd 0, 132(1)
+; ASM32PWR4-NEXT: stw 4, 140(1)
+; ASM32PWR4-NEXT: stw 3, 128(1)
; ASM32PWR4-NEXT: bl .test_fpr_stack
; ASM32PWR4-NEXT: nop
-; ASM32PWR4-NEXT: addi 1, 1, 160
+; ASM32PWR4-NEXT: addi 1, 1, 144
; ASM32PWR4-NEXT: lwz 0, 8(1)
; ASM32PWR4-NEXT: mtlr 0
; ASM32PWR4-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable.ll b/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable.ll
index ce97f37ad2b10..fb2c973351d63 100644
--- a/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable.ll
@@ -160,7 +160,7 @@ entry:
; CHECK-ASM-LABEL: .main:{{[[:space:]] *}}# %bb.0:
; CHECK-FUNC-LABEL: .csect .main[PR],5{{[[:space:]] *}}# %bb.0
; COMMON-NEXT: mflr 0
-; COMMON: stw 0, 168(1)
+; COMMON: stw 0, 152(1)
; COMMON: mtlr 0
; COMMON-NEXT: blr
; COMMON-NEXT: L..main0:
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
index 10b04b570fa32..c9890a679b4d2 100644
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
@@ -29,8 +29,8 @@
%struct.anon = type <{ i32, double }>
@astruct = global [1 x %struct.anon] [%struct.anon <{ i32 1, double 7.000000e+00 }>], align 1
-%struct.anon2 = type { double, i32 }
- at bstruct = global [1 x %struct.anon2] [%struct.anon2 { double 7.000000e+00 , i32 1}], align 8
+%struct.anon2 = type { double, i32, [4 x i8] }
+ at bstruct = global [1 x %struct.anon2] [%struct.anon2 { double 7.000000e+00 , i32 1, [4 x i8] undef }], align 8
@a = common global i32 0, align 4
@b = common global i64 0, align 8
diff --git a/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg-mir.ll b/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg-mir.ll
index 3eef8d5ff90fc..c66760a699771 100644
--- a/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg-mir.ll
+++ b/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg-mir.ll
@@ -115,23 +115,17 @@ define double @double_va_arg(double %a, ...) local_unnamed_addr {
; CHECK-NEXT: liveins: $f1, $r5, $r6, $r7, $r8, $r9, $r10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $r3 = ADDI %fixed-stack.0, 0
+ ; CHECK-NEXT: STW killed renamable $r5, 0, %fixed-stack.0 :: (store (s32) into %fixed-stack.0, align 16)
+ ; CHECK-NEXT: STW killed renamable $r6, 4, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 4)
; CHECK-NEXT: STW killed renamable $r7, 8, %fixed-stack.0 :: (store (s32), align 8)
- ; CHECK-NEXT: STW renamable $r5, 0, %fixed-stack.0 :: (store (s32) into %fixed-stack.0, align 16)
- ; CHECK-NEXT: STW renamable $r6, 4, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 4)
; CHECK-NEXT: STW killed renamable $r8, 12, %fixed-stack.0 :: (store (s32))
+ ; CHECK-NEXT: renamable $f0 = LFD 0, %fixed-stack.0 :: (load (s64) from %ir.argp.cur2, align 16)
; CHECK-NEXT: STW killed renamable $r9, 16, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 16, align 16)
; CHECK-NEXT: STW killed renamable $r10, 20, %fixed-stack.0 :: (store (s32))
- ; CHECK-NEXT: STW renamable $r3, 0, %stack.0.arg1 :: (store (s32) into %ir.arg1)
- ; CHECK-NEXT: STW killed renamable $r3, 0, %stack.1.arg2 :: (store (s32) into %ir.arg2)
- ; CHECK-NEXT: STW renamable $r5, 0, %stack.2 :: (store (s32) into %stack.2, align 8)
- ; CHECK-NEXT: STW renamable $r6, 4, %stack.2 :: (store (s32) into %stack.2 + 4)
- ; CHECK-NEXT: renamable $f0 = LFD 0, %stack.2 :: (load (s64) from %stack.2)
- ; CHECK-NEXT: STW killed renamable $r5, 0, %stack.3 :: (store (s32) into %stack.3, align 8)
- ; CHECK-NEXT: STW killed renamable $r6, 4, %stack.3 :: (store (s32) into %stack.3 + 4)
- ; CHECK-NEXT: renamable $f2 = LFD 0, %stack.3 :: (load (s64) from %stack.3)
- ; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
- ; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f2, renamable $f2, implicit $rm
- ; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
+ ; CHECK-NEXT: renamable $f1 = nofpexcept FADD renamable $f0, killed renamable $f1, implicit $rm
+ ; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, renamable $f0, implicit $rm
+ ; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f0, implicit $rm
+ ; CHECK-NEXT: STW killed renamable $r3, 0, %stack.0.arg1 :: (store (s32) into %ir.arg1)
; CHECK-NEXT: BLR implicit $lr, implicit $rm, implicit $f1
entry:
%arg1 = alloca ptr, align 4
@@ -163,31 +157,24 @@ define double @double_stack_va_arg(double %one, double %two, double %three, doub
; CHECK: bb.0.entry:
; CHECK-NEXT: liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13
; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $f0 = LFD 0, %fixed-stack.0 :: (load (s64) from %ir.argp.cur142, align 16)
+ ; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm
+ ; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f3, implicit $rm
+ ; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f4, implicit $rm
+ ; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f5, implicit $rm
+ ; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f6, implicit $rm
+ ; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f7, implicit $rm
+ ; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f8, implicit $rm
+ ; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f9, implicit $rm
+ ; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f10, implicit $rm
+ ; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f11, implicit $rm
+ ; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f12, implicit $rm
+ ; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f13, implicit $rm
+ ; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, renamable $f0, implicit $rm
+ ; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, renamable $f0, implicit $rm
+ ; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f0, implicit $rm
; CHECK-NEXT: renamable $r3 = ADDI %fixed-stack.0, 0
; CHECK-NEXT: STW killed renamable $r3, 0, %stack.0.arg1 :: (store (s32) into %ir.arg1)
- ; CHECK-NEXT: renamable $r3 = LWZ 0, %fixed-stack.0 :: (load (s32) from %ir.argp.cur142, align 16)
- ; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm
- ; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f3, implicit $rm
- ; CHECK-NEXT: STW renamable $r3, 0, %stack.2 :: (store (s32) into %stack.2, align 8)
- ; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f4, implicit $rm
- ; CHECK-NEXT: renamable $r4 = LWZ 4, %fixed-stack.0 :: (load (s32) from %ir.argp.cur142 + 4)
- ; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f5, implicit $rm
- ; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f6, implicit $rm
- ; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f7, implicit $rm
- ; CHECK-NEXT: STW renamable $r4, 4, %stack.2 :: (store (s32) into %stack.2 + 4)
- ; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f8, implicit $rm
- ; CHECK-NEXT: renamable $f1 = LFD 0, %stack.2 :: (load (s64) from %stack.2)
- ; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f9, implicit $rm
- ; CHECK-NEXT: STW killed renamable $r3, 0, %stack.3 :: (store (s32) into %stack.3, align 8)
- ; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f10, implicit $rm
- ; CHECK-NEXT: STW killed renamable $r4, 4, %stack.3 :: (store (s32) into %stack.3 + 4)
- ; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f11, implicit $rm
- ; CHECK-NEXT: renamable $f2 = LFD 0, %stack.3 :: (load (s64) from %stack.3)
- ; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f12, implicit $rm
- ; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f13, implicit $rm
- ; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
- ; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f2, renamable $f2, implicit $rm
- ; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
; CHECK-NEXT: BLR implicit $lr, implicit $rm, implicit $f1
entry:
%arg1 = alloca ptr, align 4
diff --git a/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll b/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
index 6ec56ffe3e252..4a3971082947d 100644
--- a/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
+++ b/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
@@ -108,24 +108,18 @@ entry:
define double @double_va_arg(double %a, ...) local_unnamed_addr {
; CHECK-LABEL: double_va_arg:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: stw 5, -16(1)
-; CHECK-NEXT: addi 3, 1, 32
-; CHECK-NEXT: stw 6, -12(1)
-; CHECK-NEXT: lfd 0, -16(1)
-; CHECK-NEXT: stw 5, -24(1)
-; CHECK-NEXT: fadd 0, 0, 1
-; CHECK-NEXT: stw 6, -20(1)
-; CHECK-NEXT: lfd 1, -24(1)
-; CHECK-NEXT: fadd 1, 1, 1
-; CHECK-NEXT: stw 7, 40(1)
-; CHECK-NEXT: fadd 1, 0, 1
; CHECK-NEXT: stw 5, 32(1)
+; CHECK-NEXT: addi 3, 1, 32
; CHECK-NEXT: stw 6, 36(1)
+; CHECK-NEXT: lfd 0, 32(1)
+; CHECK-NEXT: fadd 1, 0, 1
+; CHECK-NEXT: fadd 0, 0, 0
+; CHECK-NEXT: stw 7, 40(1)
; CHECK-NEXT: stw 8, 44(1)
+; CHECK-NEXT: fadd 1, 1, 0
; CHECK-NEXT: stw 9, 48(1)
; CHECK-NEXT: stw 10, 52(1)
; CHECK-NEXT: stw 3, -4(1)
-; CHECK-NEXT: stw 3, -8(1)
; CHECK-NEXT: blr
entry:
%arg1 = alloca ptr, align 4
@@ -155,31 +149,24 @@ entry:
define double @double_stack_va_arg(double %one, double %two, double %three, double %four, double %five, double %six, double %seven, double %eight, double %nine, double %ten, double %eleven, double %twelve, double %thirteen, ...) local_unnamed_addr {
; CHECK-LABEL: double_stack_va_arg:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: fadd 0, 1, 2
+; CHECK-NEXT: fadd 1, 1, 2
+; CHECK-NEXT: lfd 0, 128(1)
; CHECK-NEXT: addi 3, 1, 128
-; CHECK-NEXT: lwz 4, 132(1)
-; CHECK-NEXT: fadd 0, 0, 3
+; CHECK-NEXT: fadd 1, 1, 3
; CHECK-NEXT: stw 3, -4(1)
-; CHECK-NEXT: fadd 0, 0, 4
-; CHECK-NEXT: lwz 3, 128(1)
-; CHECK-NEXT: fadd 0, 0, 5
-; CHECK-NEXT: stw 3, -16(1)
-; CHECK-NEXT: fadd 0, 0, 6
-; CHECK-NEXT: stw 4, -12(1)
-; CHECK-NEXT: fadd 0, 0, 7
-; CHECK-NEXT: lfd 1, -16(1)
-; CHECK-NEXT: fadd 0, 0, 8
-; CHECK-NEXT: stw 3, -24(1)
-; CHECK-NEXT: fadd 0, 0, 9
-; CHECK-NEXT: stw 4, -20(1)
-; CHECK-NEXT: fadd 0, 0, 10
-; CHECK-NEXT: fadd 0, 0, 11
-; CHECK-NEXT: fadd 0, 0, 12
-; CHECK-NEXT: fadd 0, 0, 13
-; CHECK-NEXT: fadd 0, 0, 1
-; CHECK-NEXT: lfd 1, -24(1)
-; CHECK-NEXT: fadd 1, 1, 1
-; CHECK-NEXT: fadd 1, 0, 1
+; CHECK-NEXT: fadd 1, 1, 4
+; CHECK-NEXT: fadd 1, 1, 5
+; CHECK-NEXT: fadd 1, 1, 6
+; CHECK-NEXT: fadd 1, 1, 7
+; CHECK-NEXT: fadd 1, 1, 8
+; CHECK-NEXT: fadd 1, 1, 9
+; CHECK-NEXT: fadd 1, 1, 10
+; CHECK-NEXT: fadd 1, 1, 11
+; CHECK-NEXT: fadd 1, 1, 12
+; CHECK-NEXT: fadd 1, 1, 13
+; CHECK-NEXT: fadd 1, 1, 0
+; CHECK-NEXT: fadd 0, 0, 0
+; CHECK-NEXT: fadd 1, 1, 0
; CHECK-NEXT: blr
entry:
%arg1 = alloca ptr, align 4
diff --git a/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg-mir.ll b/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg-mir.ll
index 4d7c6fb6fa31e..5219e36300994 100644
--- a/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg-mir.ll
+++ b/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg-mir.ll
@@ -109,14 +109,14 @@ define double @double_va_arg(double %a, ...) local_unnamed_addr {
; CHECK-NEXT: STD renamable $x3, 0, %stack.1.arg2 :: (store (s64) into %ir.arg2)
; CHECK-NEXT: renamable $x6 = LD 0, %stack.1.arg2 :: (load (s64) from %ir.arg2)
; CHECK-NEXT: renamable $x7 = ADDI8 %fixed-stack.0, 8
+ ; CHECK-NEXT: renamable $f0 = LFD 0, %fixed-stack.0 :: (load (s64) from %fixed-stack.0)
+ ; CHECK-NEXT: renamable $x8 = ADDI8 renamable $x6, 8
; CHECK-NEXT: STD killed renamable $x4, 0, %fixed-stack.0 :: (store (s64) into %fixed-stack.0)
+ ; CHECK-NEXT: STD killed renamable $x5, 8, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 8)
; CHECK-NEXT: STD killed renamable $x3, 0, %stack.0.arg1 :: (store (s64) into %ir.arg1)
; CHECK-NEXT: STD killed renamable $x7, 0, %stack.0.arg1 :: (store (s64) into %ir.arg1)
- ; CHECK-NEXT: renamable $f0 = LFD 0, %fixed-stack.0 :: (load (s64))
- ; CHECK-NEXT: renamable $x3 = ADDI8 renamable $x6, 8
- ; CHECK-NEXT: STD killed renamable $x5, 8, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 8)
- ; CHECK-NEXT: STD killed renamable $x3, 0, %stack.1.arg2 :: (store (s64) into %ir.arg2)
- ; CHECK-NEXT: renamable $f2 = LFD 0, killed renamable $x6 :: (load (s64))
+ ; CHECK-NEXT: STD killed renamable $x8, 0, %stack.1.arg2 :: (store (s64) into %ir.arg2)
+ ; CHECK-NEXT: renamable $f2 = LFD 0, killed renamable $x6 :: (load (s64), align 4)
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f2, renamable $f2, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
@@ -145,7 +145,7 @@ define double @double_stack_va_arg(double %one, double %two, double %three, doub
; CHECK: bb.0.entry:
; CHECK-NEXT: liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $f0 = LFD 0, %fixed-stack.0 :: (load (s64))
+ ; CHECK-NEXT: renamable $f0 = LFD 0, %fixed-stack.0 :: (load (s64) from %fixed-stack.0)
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f3, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f4, implicit $rm
diff --git a/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll b/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
index 87f46fe3aca8c..16409e5ccb684 100644
--- a/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
+++ b/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
@@ -96,16 +96,16 @@ define double @double_va_arg(double %a, ...) local_unnamed_addr {
; CHECK-LABEL: double_va_arg:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi 3, 1, 56
-; CHECK-NEXT: std 4, 56(1)
-; CHECK-NEXT: std 3, -8(1)
+; CHECK-NEXT: lfd 0, 56(1)
; CHECK-NEXT: std 3, -16(1)
-; CHECK-NEXT: addi 3, 1, 64
+; CHECK-NEXT: fadd 0, 0, 1
; CHECK-NEXT: std 3, -8(1)
; CHECK-NEXT: ld 3, -16(1)
-; CHECK-NEXT: lfd 0, 56(1)
+; CHECK-NEXT: std 4, 56(1)
+; CHECK-NEXT: addi 4, 1, 64
+; CHECK-NEXT: std 4, -8(1)
; CHECK-NEXT: addi 4, 3, 8
; CHECK-NEXT: std 5, 64(1)
-; CHECK-NEXT: fadd 0, 0, 1
; CHECK-NEXT: std 6, 72(1)
; CHECK-NEXT: std 7, 80(1)
; CHECK-NEXT: std 8, 88(1)
diff --git a/llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp b/llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
index 3ab2caf702f6a..3203bb5cfdeed 100644
--- a/llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
+++ b/llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
@@ -105,7 +105,7 @@ TEST(DataLayoutUpgradeTest, ValidDataLayoutUpgrade) {
"E-m:e-Fn32-i64:64-i128:128-n32:64");
EXPECT_EQ(
UpgradeDataLayoutString("E-m:a-Fi64-i64:64-n32:64", "powerpc64-ibm-aix"),
- "E-m:a-Fi64-i64:64-i128:128-n32:64");
+ "E-m:a-Fi64-i64:64-i128:128-n32:64-f64:32:64");
// Check that WebAssembly targets add -i128:128.
EXPECT_EQ(
@@ -188,6 +188,16 @@ TEST(DataLayoutUpgradeTest, NoDataLayoutUpgrade) {
"E-m:e-Fn32-i64:64-n32");
EXPECT_EQ(UpgradeDataLayoutString("E-m:a-Fi64-i64:64-n32", "powerpc-aix"),
"E-m:a-Fi64-i64:64-n32");
+
+ EXPECT_EQ(UpgradeDataLayoutString("E-m:a-p:32:32-Fi32-i64:64-n32",
+ "powerpc-unknown-aix"),
+ "E-m:a-p:32:32-Fi32-i64:64-n32-f64:32:64");
+ EXPECT_EQ(
+ UpgradeDataLayoutString(
+ "E-m:a-Fi64-i64:64-i128:128-n32:64-S128-v256:256:256-v512:512:512",
+ "powerpc64-unknown-aix"),
+ "E-m:a-Fi64-i64:64-i128:128-n32:64-f64:32:64-S128-v256:256:256-v512:512:"
+ "512");
}
TEST(DataLayoutUpgradeTest, EmptyDataLayout) {
>From 81911be505e90c933818b796daa9738b6675230e Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov at redhat.com>
Date: Fri, 10 Oct 2025 11:02:22 +0200
Subject: [PATCH 2/2] Add additional comments
---
clang/lib/Basic/Targets/PPC.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index b538ac64e7c42..5a053e36432f8 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -390,6 +390,7 @@ class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
: PPCTargetInfo(Triple, Opts) {
if (Triple.isOSAIX())
+ // The ABI alignment for doubles on AIX is 4 bytes.
resetDataLayout("E-m:a-p:32:32-Fi32-i64:64-n32-f64:32:64");
else if (Triple.getArch() == llvm::Triple::ppcle)
resetDataLayout("e-m:e-p:32:32-Fn32-i64:64-n32");
@@ -449,6 +450,7 @@ class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
if (Triple.isOSAIX()) {
// TODO: Set appropriate ABI for AIX platform.
+ // The ABI alignment for doubles on AIX is 4 bytes.
DataLayout = "E-m:a-Fi64-i64:64-i128:128-n32:64-f64:32:64";
LongDoubleWidth = 64;
LongDoubleAlign = DoubleAlign = 32;
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