[llvm] be9e747 - [SelectionDAG] Add SDTCisSameNumEltsAs to SDTIntShiftOp. (#162756)

[via llvm-commits]

Author: Craig Topper
Date: 2025-10-09T20:50:45-07:00
New Revision: be9e747d49f7e21b97210cde6b9f458c90d2c6a4

URL: https://github.com/llvm/llvm-project/commit/be9e747d49f7e21b97210cde6b9f458c90d2c6a4
DIFF: https://github.com/llvm/llvm-project/commit/be9e747d49f7e21b97210cde6b9f458c90d2c6a4.diff

LOG: [SelectionDAG] Add SDTCisSameNumEltsAs to SDTIntShiftOp. (#162756)

The shift amount may have a different scalar size than the result, but
they should have the same number of elements or they should both
be scalar.

Added: 
    

Modified: 
    llvm/include/llvm/Target/TargetSelectionDAG.td

Removed: 
    


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diff  --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index 7bc90d4428800..774063b460495 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -116,7 +116,7 @@ def SDTIntBinOp : SDTypeProfile<1, 2, [     // add, and, or, xor, udiv, etc.
   SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
 ]>;
 def SDTIntShiftOp : SDTypeProfile<1, 2, [   // shl, sra, srl
-  SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
+  SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>, SDTCisSameNumEltsAs<0, 2>
 ]>;
 def SDTIntShiftPairOp : SDTypeProfile<2, 3, [ // shl_parts, sra_parts, srl_parts
   SDTCisInt<0>, SDTCisSameAs<1, 0>,