[llvm] 69f9138 - [RISCV] Add a new subtarget feature for throttled FP64 vector performance (#162399)

[via llvm-commits]

Author: Min-Yih Hsu
Date: 2025-10-09T17:29:29-07:00
New Revision: 69f913821d82f82cce3309da84b21375d5a128ee

URL: https://github.com/llvm/llvm-project/commit/69f913821d82f82cce3309da84b21375d5a128ee
DIFF: https://github.com/llvm/llvm-project/commit/69f913821d82f82cce3309da84b21375d5a128ee.diff

LOG: [RISCV] Add a new subtarget feature for throttled FP64 vector performance (#162399)

sifive-x390 and sifive-x280 both share the SiFIve7 scheduling model, yet
the former has a limited FP64 vector performance. Right now we account
for it by instantiating two separate scheduling models (throttled v.s.
non-throttled) from the base SiFive7 model. However, this approach
(which is also used in other performance features like fast vrgather in
SiFive7) does not scale if we add more of these performance features in
the future -- the number of scheduling models will simply become
unmanageable.

The new solution I've been working on is to let a _single_ scheduling
model be configured by subtarget features on performance features like
these, such that we no longer need to create those derived models. This
patch creates the subtarget feature that'll ultimately replace the
`isFP64Throttled` knob in SiFive7 scheduling model mentioned earlier.
There will be a follow-up patch to integrate this into the scheduling
model.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVFeatures.td
    llvm/test/CodeGen/RISCV/features-info.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 40c05e8602553..333b6938a0f53 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1823,6 +1823,11 @@ def TuneConditionalCompressedMoveFusion
 def HasConditionalMoveFusion : Predicate<"Subtarget->hasConditionalMoveFusion()">;
 def NoConditionalMoveFusion  : Predicate<"!Subtarget->hasConditionalMoveFusion()">;
 
+def TuneHasSingleElementVecFP64
+    : SubtargetFeature<"single-element-vec-fp64", "HasSingleElementVectorFP64", "true",
+                       "Certain vector FP64 operations produce a single result "
+                       "element per cycle">;
+
 def TuneMIPSP8700
     : SubtargetFeature<"mips-p8700", "RISCVProcFamily", "MIPSP8700",
                        "MIPS p8700 processor">;

diff  --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index 1a7a72d3e072b..693a40d3f39e6 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -142,6 +142,7 @@
 ; CHECK-NEXT:   shvstvecd                        - 'Shvstvecd' (vstvec supports Direct mode).
 ; CHECK-NEXT:   shxadd-load-fusion               - Enable SH(1|2|3)ADD(.UW) + load macrofusion.
 ; CHECK-NEXT:   sifive7                          - SiFive 7-Series processors.
+; CHECK-NEXT:   single-element-vec-fp64          - Certain vector FP64 operations produce a single result element per cycle.
 ; CHECK-NEXT:   smaia                            - 'Smaia' (Advanced Interrupt Architecture Machine Level).
 ; CHECK-NEXT:   smcdeleg                         - 'Smcdeleg' (Counter Delegation Machine Level).
 ; CHECK-NEXT:   smcntrpmf                        - 'Smcntrpmf' (Cycle and Instret Privilege Mode Filtering).