[llvm] e02c645 - [RISCV] Add an explicit i32 to QC_SETWMI pattern to reduce RISCVGenDAGISel.inc. NFC (#162720)

[via llvm-commits]

Author: Craig Topper
Date: 2025-10-09T14:16:21-07:00
New Revision: e02c645f9089f3fa397627043351319880d88673

URL: https://github.com/llvm/llvm-project/commit/e02c645f9089f3fa397627043351319880d88673
DIFF: https://github.com/llvm/llvm-project/commit/e02c645f9089f3fa397627043351319880d88673.diff

LOG: [RISCV] Add an explicit i32 to QC_SETWMI pattern to reduce RISCVGenDAGISel.inc. NFC (#162720)

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 447f05cf88788..f2724c411464b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1636,7 +1636,7 @@ def : QCISELECTCCIPat<SETNE,  QC_SELECTNEI>;
 }
 
 let Predicates = [HasVendorXqcilsm, IsRV32] in {
-def : Pat<(qc_setwmi GPR:$rs3, GPR:$rs1, tuimm5nonzero:$uimm5, tuimm7_lsb00:$uimm7),
+def : Pat<(qc_setwmi (i32 GPR:$rs3), GPR:$rs1, tuimm5nonzero:$uimm5, tuimm7_lsb00:$uimm7),
           (QC_SETWMI GPR:$rs3, GPR:$rs1, tuimm5nonzero:$uimm5, tuimm7_lsb00:$uimm7)>;
 } // Predicates = [HasVendorXqcilsm, IsRV32]