[llvm] [LLVM][CodeGen][SVE] ASRD cannot represent sdiv-by-one. (PR #162708)

[Paul Walker via llvm-commits]

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@@ -16248,7 +16248,9 @@ SDValue AArch64TargetLowering::LowerDIV(SDValue Op, SelectionDAG &DAG) const {
 
   bool Negated;
   uint64_t SplatVal;
-  if (Signed && isPow2Splat(Op.getOperand(1), SplatVal, Negated)) {
+  // NOTE: SRAD cannot be used to represent sdiv-by-one.
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paulwalker-arm wrote:

I plan to follow up with an NFC patch to rename the SRAD node to match the instruction it represents.

https://github.com/llvm/llvm-project/pull/162708