[llvm] [DAG] fix wrong type check in DAGCombiner::visitSRA (PR #153762)

[via llvm-commits]

woruyu wrote:

> missing test coverage

Thanks for the pointer about missing coverage.The existing tests already exercise the fold of `(sra (shl X, m), (width - n))` in general `(e.g. field-extract-use-trunc.ll, ins_subreg_coalesce-2.ll, pr49162.ll, vector-mulfix-legalize.ll)`.
The tricky part for my change is to demonstrate a difference caused by swapping `VT / TruncVT`: we need a target/type pair where isTypeLegal(VT) is true and both SIGN_EXTEND and TRUNCATE are legal/custom, so I use a script to dump these bool value in -mtriple=amdgcn-amd-amdhsa, the value like this:
```
Target triple: amdgcn-amd-amdhsa
VT,isTypeLegal,SEXT_LegalOrCustom,TRUNC_LegalOrCustom
i1,1,1,1
i128,0,1,1
i16,0,1,1
i2,0,0,0
i32,1,1,1
i4,0,0,0
i64,1,1,1
i8,0,1,1
nxv16i1,0,1,1
nxv16i16,0,1,1
nxv16i32,0,1,1
nxv16i64,0,1,1
nxv16i8,0,1,1
nxv1i1,0,1,1
nxv1i16,0,1,1
nxv1i32,0,1,1
nxv1i64,0,1,1
nxv1i8,0,1,1
nxv2i1,0,1,1
nxv2i16,0,1,1
nxv2i32,0,1,1
nxv2i64,0,1,1
nxv2i8,0,1,1
nxv32i1,0,1,1
nxv32i16,0,1,1
nxv32i32,0,1,1
nxv32i64,0,1,1
nxv32i8,0,1,1
nxv4i1,0,1,1
nxv4i16,0,1,1
nxv4i32,0,1,1
nxv4i64,0,1,1
nxv4i8,0,1,1
nxv64i1,0,1,1
nxv64i8,0,1,1
nxv8i1,0,1,1
nxv8i16,0,1,1
nxv8i32,0,1,1
nxv8i64,0,1,1
nxv8i8,0,1,1
v1024i1,0,1,1
v1024i32,0,1,1
v1024i8,0,1,1
v10i32,1,0,0
v11i32,1,0,0
v128i1,0,1,1
v128i16,0,1,1
v128i2,0,1,1
v128i32,0,1,1
v128i4,0,1,1
v128i64,0,1,1
v128i8,0,1,1
v12i32,1,0,0
v16i1,0,1,1
v16i16,0,0,0
v16i32,1,0,0
v16i64,1,0,0
v16i8,0,1,1
v1i1,0,1,1
v1i128,0,1,1
v1i16,0,1,1
v1i32,0,1,1
v1i64,0,1,1
v1i8,0,1,1
v2048i1,0,1,1
v2048i32,0,1,1
v256i1,0,1,1
v256i16,0,1,1
v256i2,0,1,1
v256i32,0,1,1
v256i64,0,1,1
v256i8,0,1,1
v2i1,0,1,1
v2i16,0,1,1
v2i32,1,1,0
v2i64,1,0,0
v2i8,0,1,1
v32i1,0,1,1
v32i16,0,0,0
v32i32,1,0,0
v32i64,0,1,1
v32i8,0,1,1
v3i1,0,1,1
v3i16,0,1,1
v3i32,1,1,0
v3i64,1,0,0
v3i8,0,1,1
v4096i1,0,1,1
v4096i16,0,1,1
v4096i32,0,1,1
v4i1,0,1,1
v4i16,0,0,0
v4i32,1,1,0
v4i64,1,0,0
v4i8,0,1,1
v512i1,0,1,1
v512i16,0,1,1
v512i32,0,1,1
v512i8,0,1,1
v5i1,0,1,1
v5i16,0,1,1
v5i32,1,1,0
v5i8,0,1,1
v64i1,0,1,1
v64i16,0,1,1
v64i32,0,1,1
v64i4,0,1,1
v64i64,0,1,1
v64i8,0,1,1
v6i1,0,1,1
v6i16,0,1,1
v6i32,1,0,0
v6i8,0,1,1
v7i1,0,1,1
v7i16,0,1,1
v7i32,1,1,0
v7i8,0,1,1
v8i1,0,1,1
v8i16,0,0,0
v8i32,1,0,0
v8i64,1,0,0
v8i8,0,1,1
v9i32,1,0,0
```
you need to find two type(the first value's bool value is 1,x,1,and the second type's bool value is 1,1,x) and the first should be transfer to the second, Obviously, you can't creat a diff testcase. Any suggestion?

https://github.com/llvm/llvm-project/pull/153762