[llvm] 33e6a9a - [IR2Vec] Added fixme for cyclic dependency in Flow-Aware embedding computation (#162522)

via llvm-commits llvm-commits at lists.llvm.org
Wed Oct 8 12:13:19 PDT 2025


Author: S. VenkataKeerthy
Date: 2025-10-08T12:13:15-07:00
New Revision: 33e6a9ae41413878cf04ff7d688e057dbd3ac256

URL: https://github.com/llvm/llvm-project/commit/33e6a9ae41413878cf04ff7d688e057dbd3ac256
DIFF: https://github.com/llvm/llvm-project/commit/33e6a9ae41413878cf04ff7d688e057dbd3ac256.diff

LOG: [IR2Vec] Added fixme for cyclic dependency in Flow-Aware embedding computation (#162522)

Added: 
    

Modified: 
    llvm/lib/Analysis/IR2Vec.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Analysis/IR2Vec.cpp b/llvm/lib/Analysis/IR2Vec.cpp
index 688535161d4b9..1794a604b991d 100644
--- a/llvm/lib/Analysis/IR2Vec.cpp
+++ b/llvm/lib/Analysis/IR2Vec.cpp
@@ -239,10 +239,21 @@ void FlowAwareEmbedder::computeEmbeddings(const BasicBlock &BB) const {
       // If the operand is defined elsewhere, we use its embedding
       if (const auto *DefInst = dyn_cast<Instruction>(Op)) {
         auto DefIt = InstVecMap.find(DefInst);
-        assert(DefIt != InstVecMap.end() &&
-               "Instruction should have been processed before its operands");
-        ArgEmb += DefIt->second;
-        continue;
+        // Fixme (#159171): Ideally we should never miss an instruction
+        // embedding here.
+        // But when we have cyclic dependencies (e.g., phi
+        // nodes), we might miss the embedding. In such cases, we fall back to
+        // using the vocabulary embedding. This can be fixed by iterating to a
+        // fixed-point, or by using a simple solver for the set of simultaneous
+        // equations.
+        // Another case when we might miss an instruction embedding is when
+        // the operand instruction is in a 
diff erent basic block that has not
+        // been processed yet. This can be fixed by processing the basic blocks
+        // in a topological order.
+        if (DefIt != InstVecMap.end())
+          ArgEmb += DefIt->second;
+        else
+          ArgEmb += Vocab[*Op];
       }
       // If the operand is not defined by an instruction, we use the vocabulary
       else {


        


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