[llvm] [llvm][RISCV] Implement Zilsd load/store pair optimization (PR #158640)

[Sam Elliott via llvm-commits]

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@@ -395,6 +423,143 @@ RISCVLoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
   return NextI;
 }
 
+//===----------------------------------------------------------------------===//
+// Post reg-alloc zilsd pass implementation
+//===----------------------------------------------------------------------===//
+
+bool RISCVLoadStoreOpt::isConsecutiveRegPair(Register First, Register Second) {
+  // Special case: both registers are zero register - this is valid for storing
+  // zeros
+  if (First == RISCV::X0 && Second == RISCV::X0)
+    return true;
+
+  // Check if registers form a valid even/odd pair for Zilsd
+  unsigned FirstNum = TRI->getEncodingValue(First);
+  unsigned SecondNum = TRI->getEncodingValue(Second);
+
+  // Must be consecutive and first must be even
+  return (FirstNum % 2 == 0) && (SecondNum == FirstNum + 1);
----------------
lenary wrote:

The case `FirstNum == 0` and `SecondNum == 1` will still return `true`.

https://github.com/llvm/llvm-project/pull/158640