[llvm] [RISCV] Factor out the core part of LMULWriteResMXVariant. NFC (PR #162347)

[Min-Yih Hsu via llvm-commits]

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@@ -567,9 +567,12 @@ multiclass SiFive7WriteResBase<int VLEN,
     defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
     defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 8, VLEN>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
-    defm  : LMULWriteResMXVariant<"WriteVLDS8",  VLDSX0Pred, [VCQ, VL],
-                                         4, [0, 1], [1, !add(1, VLDSX0Cycles)], !add(3, Cycles),
-                                         [0, 1], [1, !add(1, Cycles)], mx, IsWorstCase>;
+    defm  : LMULWriteResMXVariant<"WriteVLDS8",  VLDSX0Pred,
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mshockwave wrote:

Formatting + comment + adding the non-predicated-variant proc resources argument (i.e. the _second_ appearance of `[VCQ, VL]`) -- previously `LMULWriteResMXVariant` always uses the same proc resource for both predicated and non-predicated variant. This patch splits it so that users can customize the resources for non-predicated variant as well.

https://github.com/llvm/llvm-project/pull/162347