[llvm] [RISCV] Add IsSignExtendingOpW to Zabha and Zalasr instructions. (PR #162341)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Tue Oct 7 11:34:16 PDT 2025


https://github.com/topperc created https://github.com/llvm/llvm-project/pull/162341

None

>From 9353592a5b4935860369603a8504e5f5e7ba2b5c Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 7 Oct 2025 11:03:10 -0700
Subject: [PATCH] [RISCV] Add IsSignExtendingOpW to Zabha and Zalasr
 instructions.

---
 llvm/lib/Target/RISCV/RISCVInstrInfoZa.td     | 4 ++--
 llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
index 7cf6d5ff762ff..26313e70be60b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
@@ -140,7 +140,7 @@ def WRS_STO : WRSInst<0b000000011101, "wrs.sto">, Sched<[]>;
 // Zabha (Byte and Halfword Atomic Memory Operations)
 //===----------------------------------------------------------------------===//
 
-let Predicates = [HasStdExtZabha] in {
+let Predicates = [HasStdExtZabha], IsSignExtendingOpW = 1 in {
 defm AMOSWAP_B  : AMO_rr_aq_rl<0b00001, 0b000, "amoswap.b">,
                   Sched<[WriteAtomicB, ReadAtomicBA, ReadAtomicBD]>;
 defm AMOADD_B   : AMO_rr_aq_rl<0b00000, 0b000, "amoadd.b">,
@@ -181,7 +181,7 @@ defm AMOMAXU_H  : AMO_rr_aq_rl<0b11100, 0b001, "amomaxu.h">,
 }
 
 // If Zacas extension is also implemented, Zabha further provides AMOCAS.[B|H].
-let Predicates = [HasStdExtZabha, HasStdExtZacas] in {
+let Predicates = [HasStdExtZabha, HasStdExtZacas], IsSignExtendingOpW = 1 in {
 defm AMOCAS_B : AMO_cas_aq_rl<0b00101, 0b000, "amocas.b", GPR>;
 defm AMOCAS_H : AMO_cas_aq_rl<0b00101, 0b001, "amocas.h", GPR>;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
index 1deecd2ca6634..50ea7425437d8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
@@ -44,7 +44,7 @@ multiclass SRL_r_aq_rl<bits<3> funct3, string opcodestr> {
 // Instructions
 //===----------------------------------------------------------------------===//
 
-let Predicates = [HasStdExtZalasr] in {
+let Predicates = [HasStdExtZalasr], IsSignExtendingOpW = 1 in {
 defm LB : LAQ_r_aq_rl<0b000, "lb">;
 defm LH : LAQ_r_aq_rl<0b001, "lh">;
 defm LW : LAQ_r_aq_rl<0b010, "lw">;



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