[llvm] [AArch64][llvm] Reject assembler for invalid TLBIP instructions (PR #162090)

[Jonathan Thackray via llvm-commits]

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@@ -830,131 +851,151 @@ class TLBIEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm,
   code RequiresStr = [{ { }] # !interleave(Requires # ExtraRequires, [{, }]) # [{ } }];
 }
 
+def TLBIPTable : GenericTable {
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jthackray wrote:

Thanks, good idea, done.

https://github.com/llvm/llvm-project/pull/162090