[llvm] [SPIR-V] Add SPV_INTEL_predicated_io extension (PR #161591)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 7 07:55:28 PDT 2025
https://github.com/YixingZhang007 updated https://github.com/llvm/llvm-project/pull/161591
>From 704d31bbed8f5d0f0ebe4726a8d8b0a1e29a0333 Mon Sep 17 00:00:00 2001
From: "Zhang, Yixing" <yixing.zhang at intel.com>
Date: Wed, 1 Oct 2025 13:04:17 -0700
Subject: [PATCH 1/9] add support for SPV_INTEL_predicated_io extension
---
llvm/docs/SPIRVUsage.rst | 2 ++
llvm/lib/Target/SPIRV/SPIRVBuiltins.td | 5 +++++
llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp | 3 ++-
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 6 ++++++
llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td | 2 ++
5 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/llvm/docs/SPIRVUsage.rst b/llvm/docs/SPIRVUsage.rst
index b6cd4b4feb46b..d2d66462b5df9 100644
--- a/llvm/docs/SPIRVUsage.rst
+++ b/llvm/docs/SPIRVUsage.rst
@@ -233,6 +233,8 @@ Below is a list of supported SPIR-V extensions, sorted alphabetically by their e
- Adds support for 4-bit integer type, and allow this type to be used in cooperative matrices.
* - ``SPV_KHR_float_controls2``
- Adds execution modes and decorations to control floating-point computations in both kernels and shaders. It can be used on whole modules and individual instructions.
+ * - ``SPV_INTEL_predicated_io``
+ - Adds predicated load and store instructions that conditionally read from or write to memory based on a boolean predicate.
SPIR-V representation in LLVM IR
================================
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
index 2a8deb6bf498b..c4d1d36eb9a5d 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
@@ -70,6 +70,7 @@ def BindlessINTEL : BuiltinGroup;
def TernaryBitwiseINTEL : BuiltinGroup;
def Block2DLoadStore : BuiltinGroup;
def Pipe : BuiltinGroup;
+def PredicatedIO : BuiltinGroup;
//===----------------------------------------------------------------------===//
// Class defining a demangled builtin record. The information in the record
@@ -752,6 +753,10 @@ defm : DemangledNativeBuiltin<"__spirv_Subgroup2DBlockLoadTransformINTEL", OpenC
defm : DemangledNativeBuiltin<"__spirv_Subgroup2DBlockPrefetchINTEL", OpenCL_std, Block2DLoadStore, 9, 9, OpSubgroup2DBlockPrefetchINTEL>;
defm : DemangledNativeBuiltin<"__spirv_Subgroup2DBlockStoreINTEL", OpenCL_std, Block2DLoadStore, 10, 10, OpSubgroup2DBlockStoreINTEL>;
+// SPV_INTEL_predicated_io builtin records
+defm : DemangledNativeBuiltin<"__spirv_PredicatedLoadINTEL", OpenCL_std, PredicatedIO, 3, 4, OpPredicatedLoadINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_PredicatedStoreINTEL", OpenCL_std, PredicatedIO, 3, 4, OpPredicatedStoreINTEL>;
+
//===----------------------------------------------------------------------===//
// Class defining a work/sub group builtin that should be translated into a
// SPIR-V instruction using the defined properties.
diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
index 85ea9e156cb97..b7f984398559c 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
@@ -151,7 +151,8 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
{"SPV_KHR_bfloat16", SPIRV::Extension::Extension::SPV_KHR_bfloat16},
{"SPV_EXT_relaxed_printf_string_address_space",
SPIRV::Extension::Extension::
- SPV_EXT_relaxed_printf_string_address_space}};
+ SPV_EXT_relaxed_printf_string_address_space}},
+ {"SPV_INTEL_predicated_io", SPIRV::Extension::Extension::SPV_INTEL_predicated_io};
bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
StringRef ArgValue,
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 1723bfb639189..2304db952f0de 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -987,3 +987,9 @@ def OpSubgroup2DBlockPrefetchINTEL: Op<6234, (outs), (ins ID:$element_size, ID:$
def OpSubgroup2DBlockStoreINTEL: Op<6235, (outs), (ins ID:$element_size, ID:$block_width, ID:$block_height,
ID:$block_count, ID:$src_ptr, ID:$dst_base_ptr, ID:$memory_width, ID:$memory_height, ID:$memory_pitch, ID:$coord),
"OpSubgroup2DBlockStoreINTEL $element_size $block_width $block_height $block_count $src_ptr $dst_base_ptr $memory_width $memory_height $memory_pitch $coord">;
+
+// SPV_INTEL_predicated_io
+def OpPredicatedLoadINTEL: Op<6528, (outs ID:$res), (ins ID:$ptr, ID:$predicate, ID:$default_value),
+ "$res = OpPredicatedLoadINTEL $ptr $predicate $default_value">;
+def OpPredicatedStoreINTEL: Op<6529, (outs), (ins ID:$ptr, ID:$object, ID:$predicate),
+ "OpPredicatedStoreINTEL $ptr $object $predicate">;
diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
index 6a32dbabff3d3..26256429537e9 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
@@ -385,6 +385,7 @@ defm SPV_INTEL_int4 : ExtensionOperand<123, [EnvOpenCL]>;
defm SPV_KHR_float_controls2 : ExtensionOperand<124, [EnvVulkan, EnvOpenCL]>;
defm SPV_INTEL_tensor_float32_conversion : ExtensionOperand<125, [EnvOpenCL]>;
defm SPV_KHR_bfloat16 : ExtensionOperand<126, [EnvVulkan, EnvOpenCL]>;
+defm SPV_INTEL_predicated_io : ExtensionOperand<127, [EnvOpenCL]>;
//===----------------------------------------------------------------------===//
// Multiclass used to define Capabilities enum values and at the same time
@@ -594,6 +595,7 @@ defm SubgroupMatrixMultiplyAccumulateINTEL : CapabilityOperand<6236, 0, 0, [SPV_
defm Subgroup2DBlockIOINTEL : CapabilityOperand<6228, 0, 0, [SPV_INTEL_2d_block_io], []>;
defm Subgroup2DBlockTransformINTEL : CapabilityOperand<6229, 0, 0, [SPV_INTEL_2d_block_io], [Subgroup2DBlockIOINTEL]>;
defm Subgroup2DBlockTransposeINTEL : CapabilityOperand<6230, 0, 0, [SPV_INTEL_2d_block_io], [Subgroup2DBlockIOINTEL]>;
+defm PredicatedIOINTEL : CapabilityOperand<6257, 0, 0, [SPV_INTEL_predicated_io], []>;
defm Int4TypeINTEL : CapabilityOperand<5112, 0, 0, [SPV_INTEL_int4], []>;
defm Int4CooperativeMatrixINTEL : CapabilityOperand<5114, 0, 0, [SPV_INTEL_int4], [Int4TypeINTEL, CooperativeMatrixKHR]>;
defm TensorFloat32RoundingINTEL : CapabilityOperand<6425, 0, 0, [SPV_INTEL_tensor_float32_conversion], []>;
>From 1416ead05762053ee949f146fa9afaa0fa3fd071 Mon Sep 17 00:00:00 2001
From: "Zhang, Yixing" <yixing.zhang at intel.com>
Date: Wed, 1 Oct 2025 15:12:12 -0700
Subject: [PATCH 2/9] add the test and the rest of the implememtation
---
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 31 +++++++++++++++++++
llvm/lib/Target/SPIRV/SPIRVBuiltins.td | 6 ++--
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 11 +++++++
3 files changed, 45 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 0e0c4547c751e..b648271a01d75 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -1096,6 +1096,25 @@ static bool build2DBlockIOINTELInst(const SPIRV::IncomingCall *Call,
return true;
}
+// Helper function for building Intel's predicated load/store instructions.
+static bool buildPredicatedLoadStoreInst(const SPIRV::IncomingCall *Call,
+ unsigned Opcode,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ // Generate SPIRV instruction accordingly.
+ if (Call->isSpirvOp())
+ return buildOpFromWrapper(MIRBuilder, Opcode, Call,
+ GR->getSPIRVTypeID(Call->ReturnType));
+
+ auto MIB = MIRBuilder.buildInstr(Opcode)
+ .addDef(Call->ReturnRegister)
+ .addUse(GR->getSPIRVTypeID(Call->ReturnType));
+ for (unsigned i = 0; i < Call->Arguments.size(); ++i)
+ MIB.addUse(Call->Arguments[i]);
+
+ return true;
+}
+
static bool buildPipeInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
unsigned Scope, MachineIRBuilder &MIRBuilder,
SPIRVGlobalRegistry *GR) {
@@ -2419,6 +2438,16 @@ static bool generatePipeInst(const SPIRV::IncomingCall *Call,
return buildPipeInst(Call, Opcode, Scope, MIRBuilder, GR);
}
+static bool generatePredicatedLoadStoreInst(const SPIRV::IncomingCall *Call,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ const SPIRV::DemangledBuiltin *Builtin = Call->Builtin;
+ unsigned Opcode =
+ SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode;
+
+ return buildPredicatedLoadStoreInst(Call, Opcode, MIRBuilder, GR);
+}
+
static bool buildNDRange(const SPIRV::IncomingCall *Call,
MachineIRBuilder &MIRBuilder,
SPIRVGlobalRegistry *GR) {
@@ -3019,6 +3048,8 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
return generate2DBlockIOINTELInst(Call.get(), MIRBuilder, GR);
case SPIRV::Pipe:
return generatePipeInst(Call.get(), MIRBuilder, GR);
+ case SPIRV::PredicatedLoadStore:
+ return generatePredicatedLoadStoreInst(Call.get(), MIRBuilder, GR);
}
return false;
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
index c4d1d36eb9a5d..3b8764a6401c6 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
@@ -70,7 +70,7 @@ def BindlessINTEL : BuiltinGroup;
def TernaryBitwiseINTEL : BuiltinGroup;
def Block2DLoadStore : BuiltinGroup;
def Pipe : BuiltinGroup;
-def PredicatedIO : BuiltinGroup;
+def PredicatedLoadStore : BuiltinGroup;
//===----------------------------------------------------------------------===//
// Class defining a demangled builtin record. The information in the record
@@ -754,8 +754,8 @@ defm : DemangledNativeBuiltin<"__spirv_Subgroup2DBlockPrefetchINTEL", OpenCL_std
defm : DemangledNativeBuiltin<"__spirv_Subgroup2DBlockStoreINTEL", OpenCL_std, Block2DLoadStore, 10, 10, OpSubgroup2DBlockStoreINTEL>;
// SPV_INTEL_predicated_io builtin records
-defm : DemangledNativeBuiltin<"__spirv_PredicatedLoadINTEL", OpenCL_std, PredicatedIO, 3, 4, OpPredicatedLoadINTEL>;
-defm : DemangledNativeBuiltin<"__spirv_PredicatedStoreINTEL", OpenCL_std, PredicatedIO, 3, 4, OpPredicatedStoreINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_PredicatedLoadINTEL", OpenCL_std, PredicatedLoadStore, 3, 4, OpPredicatedLoadINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_PredicatedStoreINTEL", OpenCL_std, PredicatedLoadStore, 3, 4, OpPredicatedStoreINTEL>;
//===----------------------------------------------------------------------===//
// Class defining a work/sub group builtin that should be translated into a
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index dc717a6ca5870..5144fb14fa6a6 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -2035,6 +2035,17 @@ void addInstrRequirements(const MachineInstr &MI,
// TODO: Add UntypedPointersKHR when implemented.
break;
}
+ case SPIRV::OpPredicatedLoadINTEL:
+ case SPIRV::OpPredicatedStoreINTEL: {
+ if (!ST.canUseExtension(SPIRV::Extension::SPV_INTEL_predicated_io))
+ report_fatal_error(
+ "OpPredicated[Load/Store]INTEL instructions require "
+ "the following SPIR-V extension: SPV_INTEL_predicated_io",
+ false);
+ Reqs.addExtension(SPIRV::Extension::SPV_INTEL_predicated_io);
+ Reqs.addCapability(SPIRV::Capability::PredicatedIOINTEL);
+ break;
+ }
default:
break;
>From cf7d398db70a618e6f2d34b3908b1766bdd871b4 Mon Sep 17 00:00:00 2001
From: "Zhang, Yixing" <yixing.zhang at intel.com>
Date: Fri, 3 Oct 2025 14:05:35 -0700
Subject: [PATCH 3/9] Add test fot the extension
---
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 37 +++----
llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp | 4 +-
.../extensions/SPV_INTEL_predicated_io/2 | 104 ++++++++++++++++++
.../predicated_io_generic.ll | 38 +++++++
4 files changed, 162 insertions(+), 21 deletions(-)
create mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/2
create mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index b648271a01d75..7d72317409197 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -1096,25 +1096,6 @@ static bool build2DBlockIOINTELInst(const SPIRV::IncomingCall *Call,
return true;
}
-// Helper function for building Intel's predicated load/store instructions.
-static bool buildPredicatedLoadStoreInst(const SPIRV::IncomingCall *Call,
- unsigned Opcode,
- MachineIRBuilder &MIRBuilder,
- SPIRVGlobalRegistry *GR) {
- // Generate SPIRV instruction accordingly.
- if (Call->isSpirvOp())
- return buildOpFromWrapper(MIRBuilder, Opcode, Call,
- GR->getSPIRVTypeID(Call->ReturnType));
-
- auto MIB = MIRBuilder.buildInstr(Opcode)
- .addDef(Call->ReturnRegister)
- .addUse(GR->getSPIRVTypeID(Call->ReturnType));
- for (unsigned i = 0; i < Call->Arguments.size(); ++i)
- MIB.addUse(Call->Arguments[i]);
-
- return true;
-}
-
static bool buildPipeInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
unsigned Scope, MachineIRBuilder &MIRBuilder,
SPIRVGlobalRegistry *GR) {
@@ -1150,6 +1131,24 @@ static bool buildPipeInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
}
}
+// Helper function for building Intel's predicated load/store instructions.
+static bool buildPredicatedLoadStoreInst(const SPIRV::IncomingCall *Call,
+ unsigned Opcode,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ // Generate SPIRV instruction accordingly.
+ if (Call->isSpirvOp())
+ return buildOpFromWrapper(MIRBuilder, Opcode, Call, Register(0));
+
+ auto MIB = MIRBuilder.buildInstr(Opcode)
+ .addDef(Call->ReturnRegister)
+ .addUse(GR->getSPIRVTypeID(Call->ReturnType));
+ for (unsigned i = 0; i < Call->Arguments.size(); ++i)
+ MIB.addUse(Call->Arguments[i]);
+
+ return true;
+}
+
static unsigned getNumComponentsForDim(SPIRV::Dim::Dim dim) {
switch (dim) {
case SPIRV::Dim::DIM_1D:
diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
index b7f984398559c..60bf001fe933c 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
@@ -151,8 +151,8 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
{"SPV_KHR_bfloat16", SPIRV::Extension::Extension::SPV_KHR_bfloat16},
{"SPV_EXT_relaxed_printf_string_address_space",
SPIRV::Extension::Extension::
- SPV_EXT_relaxed_printf_string_address_space}},
- {"SPV_INTEL_predicated_io", SPIRV::Extension::Extension::SPV_INTEL_predicated_io};
+ SPV_EXT_relaxed_printf_string_address_space},
+ {"SPV_INTEL_predicated_io", SPIRV::Extension::Extension::SPV_INTEL_predicated_io}};
bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
StringRef ArgValue,
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/2 b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/2
new file mode 100644
index 0000000000000..0d89b35e8b158
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/2
@@ -0,0 +1,104 @@
+
+# After IRTranslator
+# Machine code for function foo: IsSSA, TracksLiveness
+
+bb.1.entry:
+ %6:type(s64) = OpTypePointer 5, %5:type(s64)
+ %7:type(s64) = OpTypeBool
+ %9:type(s64) = OpTypeVoid
+ %10:type(s64) = OpTypeFunction %9:type(s64), %6:type(s64), %6:type(s64), %5:type(s64), %5:type(s64), %7:type(s64)
+ %5:type(s64) = OpTypeInt 32, 0
+ OpName %0:pid(p1), 1684107116, 1768910943, 1919251566, 0
+ OpName %1:pid(p1), 1919906931, 1869635429, 1702129257, 114
+ OpName %2:iid(s32), 1634100580, 1601465461, 1970037110, 101
+ OpName %3:iid(s32), 1919906931, 1651466085, 1952671082, 0
+ OpName %4:iid(s1), 1684370032, 1952539497, 101
+ OpDecorate %4:iid(s1), 38, 0
+ %8:iid(s64) = OpFunction %9:type(s64), 0, %10:type(s64)
+ %0:pid(p1) = OpFunctionParameter %6:type(s64)
+ %1:pid(p1) = OpFunctionParameter %6:type(s64)
+ %2:iid(s32) = OpFunctionParameter %5:type(s64)
+ %3:iid(s32) = OpFunctionParameter %5:type(s64)
+ %4:iid(s1) = OpFunctionParameter %7:type(s64)
+ OpName %8:iid(s64), 7303014
+ OpDecorate %8:iid(s64), 41, 7303014, 0
+ %13:iid(s32) = G_CONSTANT i32 0
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.assign.ptr.type), %0:pid(p1), <0x63fe33472928>, 1
+ OpPredicatedLoadINTEL %0:pid(p1), %4:iid(s1), %2:iid(s32)
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.assign.type), %11:iid(s32), <0x63fe33472928>
+ OpPredicatedLoadINTEL %0:pid(p1), %4:iid(s1), %2:iid(s32), %13:iid(s32)
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.assign.type), %12:iid(s32), <0x63fe33472928>
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.assign.ptr.type), %1:pid(p1), <0x63fe33472928>, 1
+ OpPredicatedStoreINTEL %1:pid(p1), %3:iid(s32), %4:iid(s1)
+ OpPredicatedStoreINTEL %1:pid(p1), %3:iid(s32), %4:iid(s1), %13:iid(s32)
+ OpReturn
+
+# End machine code for function foo.
+
+*** Bad machine code: Too few operands ***
+- function: foo
+- basic block: %bb.1 entry (0x63fe334751e8)
+- instruction: OpPredicatedLoadINTEL %0:pid(p1), %4:iid(s1), %2:iid(s32)
+4 operands expected, but 3 given.
+
+*** Bad machine code: Explicit definition marked as use ***
+- function: foo
+- basic block: %bb.1 entry (0x63fe334751e8)
+- instruction: OpPredicatedLoadINTEL %0:pid(p1), %4:iid(s1), %2:iid(s32)
+- operand 0: %0:pid
+
+*** Bad machine code: Reading virtual register without a def ***
+- function: foo
+- basic block: %bb.1 entry (0x63fe334751e8)
+- instruction: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.assign.type), %11:iid(s32), <0x63fe33472928>
+- operand 1: %11:iid
+
+*** Bad machine code: Explicit definition marked as use ***
+- function: foo
+- basic block: %bb.1 entry (0x63fe334751e8)
+- instruction: OpPredicatedLoadINTEL %0:pid(p1), %4:iid(s1), %2:iid(s32), %13:iid(s32)
+- operand 0: %0:pid
+
+*** Bad machine code: Reading virtual register without a def ***
+- function: foo
+- basic block: %bb.1 entry (0x63fe334751e8)
+- instruction: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.assign.type), %12:iid(s32), <0x63fe33472928>
+- operand 1: %12:iid
+
+*** Bad machine code: Extra explicit operand on non-variadic instruction ***
+- function: foo
+- basic block: %bb.1 entry (0x63fe334751e8)
+- instruction: OpPredicatedStoreINTEL %1:pid(p1), %3:iid(s32), %4:iid(s1), %13:iid(s32)
+- operand 3: %13:iid
+LLVM ERROR: Found 6 machine code errors.
+PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
+Stack dump:
+0. Program arguments: llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_predicated_io predicated_io_generic.ll -o 1
+1. Running pass 'Function Pass Manager' on module 'predicated_io_generic.ll'.
+2. Running pass 'Verify generated machine code' on function '@foo'
+ #0 0x000063fe28fe129e llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/Support/Unix/Signals.inc:834:22
+ #1 0x000063fe28fe171f PrintStackTraceSignalHandler(void*) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/Support/Unix/Signals.inc:917:1
+ #2 0x000063fe28fde897 llvm::sys::RunSignalHandlers() /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/Support/Signals.cpp:104:20
+ #3 0x000063fe28fe0adb SignalHandler(int, siginfo_t*, void*) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/Support/Unix/Signals.inc:426:14
+ #4 0x00007fd7bc445320 (/lib/x86_64-linux-gnu/libc.so.6+0x45320)
+ #5 0x00007fd7bc49eb1c __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
+ #6 0x00007fd7bc49eb1c __pthread_kill_internal ./nptl/pthread_kill.c:78:10
+ #7 0x00007fd7bc49eb1c pthread_kill ./nptl/pthread_kill.c:89:10
+ #8 0x00007fd7bc44526e raise ./signal/../sysdeps/posix/raise.c:27:6
+ #9 0x00007fd7bc4288ff abort ./stdlib/abort.c:81:7
+#10 0x000063fe28ef122a llvm::report_fatal_error(llvm::Twine const&, bool) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/Support/ErrorHandling.cpp:137:9
+#11 0x000063fe279b127e (anonymous namespace)::MachineVerifier::ReportedErrors::~ReportedErrors() /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/CodeGen/MachineVerifier.cpp:262:33
+#12 0x000063fe279b1416 (anonymous namespace)::MachineVerifier::~MachineVerifier() /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/CodeGen/MachineVerifier.cpp:102:8
+#13 0x000063fe279b155c (anonymous namespace)::MachineVerifierLegacyPass::runOnMachineFunction(llvm::MachineFunction&) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/CodeGen/MachineVerifier.cpp:390:12
+#14 0x000063fe27814feb llvm::MachineFunctionPass::runOnFunction(llvm::Function&) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/CodeGen/MachineFunctionPass.cpp:108:30
+#15 0x000063fe2813b39a llvm::FPPassManager::runOnFunction(llvm::Function&) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1398:20
+#16 0x000063fe2813b670 llvm::FPPassManager::runOnModule(llvm::Module&) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1444:13
+#17 0x000063fe2813bacf (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1513:20
+#18 0x000063fe28136a5a llvm::legacy::PassManagerImpl::run(llvm::Module&) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:531:13
+#19 0x000063fe2813c3c5 llvm::legacy::PassManager::run(llvm::Module&) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1641:1
+#20 0x000063fe2416b360 compileModule(char**, llvm::LLVMContext&) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/tools/llc/llc.cpp:761:34
+#21 0x000063fe24168941 main /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/tools/llc/llc.cpp:404:35
+#22 0x00007fd7bc42a1ca __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:74:3
+#23 0x00007fd7bc42a28b call_init ./csu/../csu/libc-start.c:128:20
+#24 0x00007fd7bc42a28b __libc_start_main ./csu/../csu/libc-start.c:347:5
+#25 0x000063fe24167425 _start (/localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/build/bin/llc+0xbbc425)
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll
new file mode 100644
index 0000000000000..f176903860e31
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll
@@ -0,0 +1,38 @@
+; RUN: not llc -O0 -mtriple=spirv64-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_predicated_io %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s --spirv-ext=+SPV_INTEL_predicated_io -o - -filetype=obj | spirv-val %}
+
+; CHECK-ERROR: LLVM ERROR: OpPredicated[Load/Store]INTEL
+; CHECK-ERROR-SAME: instructions require the following SPIR-V extension: SPV_INTEL_predicated_io
+
+; CHECK-DAG: Capability PredicatedIOINTEL
+; CHECK-DAG: Extension "SPV_INTEL_predicated_io"
+
+; CHECK-DAG: %[[Int32Ty:[0-9]+]] = OpTypeInt 32 0
+; CHECK-DAG: %[[Const0:[0-9]+]] = OpConstant %[[Int32Ty]] 0
+; CHECK-DAG: %[[VoidTy:[0-9]+]] = OpTypeVoid
+; CHECK-DAG: %[[IntPtrTy:[0-9]+]] = OpTypePointer CrossWorkgroup %[[Int32Ty]]
+; CHECK-DAG: %[[BoolTy:[0-9]+]] = OpTypeBool
+; CHECK: %[[LoadPtr:]] = FunctionParameter %[[IntPtrTy]]
+; CHECK: %[[StorePtr:]] = FunctionParameter %[[IntPtrTy]]
+; CHECK: %[[DefaultVal:]] = FunctionParameter %[[Int32Ty]]
+; CHECK: %[[StoreObj:]] = FunctionParameter %[[Int32Ty]]
+; CHECK: %[[Predicate:]] = FunctionParameter %[[BoolTy]]
+; CHECK: PredicatedLoadINTEL %[[Int32Ty]] %[[Result1:]] %[[LoadPtr]] %[[Predicate]] %[[DefaultVal]]
+; CHECK: PredicatedLoadINTEL %[[Int32Ty]] %[[Result2:]] %[[LoadPtr]] %[[Predicate]] %[[DefaultVal]] %[[Const0]]
+; CHECK: PredicatedStoreINTEL %[[StorePtr]] %[[StoreObj]] %[[Predicate]]
+; CHECK: PredicatedStoreINTEL %[[StorePtr]] %[[StoreObj]] %[[Predicate]] %[[Const0]]
+
+define spir_func void @foo(ptr addrspace(1) %load_pointer, ptr addrspace(1) %store_pointer, i32 %default_value, i32 %store_object, i1 zeroext %predicate) {
+entry:
+ %1 = call spir_func i32 @_Z27__spirv_PredicatedLoadINTELPU3AS1Kibi(ptr addrspace(1) %load_pointer, i1 %predicate, i32 %default_value)
+ %2 = call spir_func i32 @_Z27__spirv_PredicatedLoadINTELPU3AS1Kibii(ptr addrspace(1) %load_pointer, i1 %predicate, i32 %default_value, i32 0)
+ call spir_func void @_Z28__spirv_PredicatedStoreINTELPU3AS1Kiib(ptr addrspace(1) %store_pointer, i32 %store_object, i1 %predicate)
+ call spir_func void @_Z28__spirv_PredicatedStoreINTELPU3AS1Kiibi(ptr addrspace(1) %store_pointer, i32 %store_object, i1 %predicate, i32 0)
+ ret void
+}
+
+declare spir_func i32 @_Z27__spirv_PredicatedLoadINTELPU3AS1Kibi(ptr addrspace(1), i1, i32)
+declare spir_func i32 @_Z27__spirv_PredicatedLoadINTELPU3AS1Kibii(ptr addrspace(1), i1, i32, i32)
+declare spir_func void @_Z28__spirv_PredicatedStoreINTELPU3AS1Kiib(ptr addrspace(1), i32, i1)
+declare spir_func void @_Z28__spirv_PredicatedStoreINTELPU3AS1Kiibi(ptr addrspace(1), i32, i1, i32)
>From 845c0e88fca929244a8bfe34e55b3105f205f128 Mon Sep 17 00:00:00 2001
From: "Zhang, Yixing" <yixing.zhang at intel.com>
Date: Fri, 3 Oct 2025 14:06:44 -0700
Subject: [PATCH 4/9] remove debug file
---
.../extensions/SPV_INTEL_predicated_io/2 | 104 ------------------
1 file changed, 104 deletions(-)
delete mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/2
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/2 b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/2
deleted file mode 100644
index 0d89b35e8b158..0000000000000
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/2
+++ /dev/null
@@ -1,104 +0,0 @@
-
-# After IRTranslator
-# Machine code for function foo: IsSSA, TracksLiveness
-
-bb.1.entry:
- %6:type(s64) = OpTypePointer 5, %5:type(s64)
- %7:type(s64) = OpTypeBool
- %9:type(s64) = OpTypeVoid
- %10:type(s64) = OpTypeFunction %9:type(s64), %6:type(s64), %6:type(s64), %5:type(s64), %5:type(s64), %7:type(s64)
- %5:type(s64) = OpTypeInt 32, 0
- OpName %0:pid(p1), 1684107116, 1768910943, 1919251566, 0
- OpName %1:pid(p1), 1919906931, 1869635429, 1702129257, 114
- OpName %2:iid(s32), 1634100580, 1601465461, 1970037110, 101
- OpName %3:iid(s32), 1919906931, 1651466085, 1952671082, 0
- OpName %4:iid(s1), 1684370032, 1952539497, 101
- OpDecorate %4:iid(s1), 38, 0
- %8:iid(s64) = OpFunction %9:type(s64), 0, %10:type(s64)
- %0:pid(p1) = OpFunctionParameter %6:type(s64)
- %1:pid(p1) = OpFunctionParameter %6:type(s64)
- %2:iid(s32) = OpFunctionParameter %5:type(s64)
- %3:iid(s32) = OpFunctionParameter %5:type(s64)
- %4:iid(s1) = OpFunctionParameter %7:type(s64)
- OpName %8:iid(s64), 7303014
- OpDecorate %8:iid(s64), 41, 7303014, 0
- %13:iid(s32) = G_CONSTANT i32 0
- G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.assign.ptr.type), %0:pid(p1), <0x63fe33472928>, 1
- OpPredicatedLoadINTEL %0:pid(p1), %4:iid(s1), %2:iid(s32)
- G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.assign.type), %11:iid(s32), <0x63fe33472928>
- OpPredicatedLoadINTEL %0:pid(p1), %4:iid(s1), %2:iid(s32), %13:iid(s32)
- G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.assign.type), %12:iid(s32), <0x63fe33472928>
- G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.assign.ptr.type), %1:pid(p1), <0x63fe33472928>, 1
- OpPredicatedStoreINTEL %1:pid(p1), %3:iid(s32), %4:iid(s1)
- OpPredicatedStoreINTEL %1:pid(p1), %3:iid(s32), %4:iid(s1), %13:iid(s32)
- OpReturn
-
-# End machine code for function foo.
-
-*** Bad machine code: Too few operands ***
-- function: foo
-- basic block: %bb.1 entry (0x63fe334751e8)
-- instruction: OpPredicatedLoadINTEL %0:pid(p1), %4:iid(s1), %2:iid(s32)
-4 operands expected, but 3 given.
-
-*** Bad machine code: Explicit definition marked as use ***
-- function: foo
-- basic block: %bb.1 entry (0x63fe334751e8)
-- instruction: OpPredicatedLoadINTEL %0:pid(p1), %4:iid(s1), %2:iid(s32)
-- operand 0: %0:pid
-
-*** Bad machine code: Reading virtual register without a def ***
-- function: foo
-- basic block: %bb.1 entry (0x63fe334751e8)
-- instruction: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.assign.type), %11:iid(s32), <0x63fe33472928>
-- operand 1: %11:iid
-
-*** Bad machine code: Explicit definition marked as use ***
-- function: foo
-- basic block: %bb.1 entry (0x63fe334751e8)
-- instruction: OpPredicatedLoadINTEL %0:pid(p1), %4:iid(s1), %2:iid(s32), %13:iid(s32)
-- operand 0: %0:pid
-
-*** Bad machine code: Reading virtual register without a def ***
-- function: foo
-- basic block: %bb.1 entry (0x63fe334751e8)
-- instruction: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.assign.type), %12:iid(s32), <0x63fe33472928>
-- operand 1: %12:iid
-
-*** Bad machine code: Extra explicit operand on non-variadic instruction ***
-- function: foo
-- basic block: %bb.1 entry (0x63fe334751e8)
-- instruction: OpPredicatedStoreINTEL %1:pid(p1), %3:iid(s32), %4:iid(s1), %13:iid(s32)
-- operand 3: %13:iid
-LLVM ERROR: Found 6 machine code errors.
-PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
-Stack dump:
-0. Program arguments: llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_predicated_io predicated_io_generic.ll -o 1
-1. Running pass 'Function Pass Manager' on module 'predicated_io_generic.ll'.
-2. Running pass 'Verify generated machine code' on function '@foo'
- #0 0x000063fe28fe129e llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/Support/Unix/Signals.inc:834:22
- #1 0x000063fe28fe171f PrintStackTraceSignalHandler(void*) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/Support/Unix/Signals.inc:917:1
- #2 0x000063fe28fde897 llvm::sys::RunSignalHandlers() /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/Support/Signals.cpp:104:20
- #3 0x000063fe28fe0adb SignalHandler(int, siginfo_t*, void*) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/Support/Unix/Signals.inc:426:14
- #4 0x00007fd7bc445320 (/lib/x86_64-linux-gnu/libc.so.6+0x45320)
- #5 0x00007fd7bc49eb1c __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
- #6 0x00007fd7bc49eb1c __pthread_kill_internal ./nptl/pthread_kill.c:78:10
- #7 0x00007fd7bc49eb1c pthread_kill ./nptl/pthread_kill.c:89:10
- #8 0x00007fd7bc44526e raise ./signal/../sysdeps/posix/raise.c:27:6
- #9 0x00007fd7bc4288ff abort ./stdlib/abort.c:81:7
-#10 0x000063fe28ef122a llvm::report_fatal_error(llvm::Twine const&, bool) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/Support/ErrorHandling.cpp:137:9
-#11 0x000063fe279b127e (anonymous namespace)::MachineVerifier::ReportedErrors::~ReportedErrors() /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/CodeGen/MachineVerifier.cpp:262:33
-#12 0x000063fe279b1416 (anonymous namespace)::MachineVerifier::~MachineVerifier() /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/CodeGen/MachineVerifier.cpp:102:8
-#13 0x000063fe279b155c (anonymous namespace)::MachineVerifierLegacyPass::runOnMachineFunction(llvm::MachineFunction&) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/CodeGen/MachineVerifier.cpp:390:12
-#14 0x000063fe27814feb llvm::MachineFunctionPass::runOnFunction(llvm::Function&) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/CodeGen/MachineFunctionPass.cpp:108:30
-#15 0x000063fe2813b39a llvm::FPPassManager::runOnFunction(llvm::Function&) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1398:20
-#16 0x000063fe2813b670 llvm::FPPassManager::runOnModule(llvm::Module&) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1444:13
-#17 0x000063fe2813bacf (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1513:20
-#18 0x000063fe28136a5a llvm::legacy::PassManagerImpl::run(llvm::Module&) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:531:13
-#19 0x000063fe2813c3c5 llvm::legacy::PassManager::run(llvm::Module&) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1641:1
-#20 0x000063fe2416b360 compileModule(char**, llvm::LLVMContext&) /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/tools/llc/llc.cpp:761:34
-#21 0x000063fe24168941 main /localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/llvm/tools/llc/llc.cpp:404:35
-#22 0x00007fd7bc42a1ca __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:74:3
-#23 0x00007fd7bc42a28b call_init ./csu/../csu/libc-start.c:128:20
-#24 0x00007fd7bc42a28b __libc_start_main ./csu/../csu/libc-start.c:347:5
-#25 0x000063fe24167425 _start (/localdisk3/yixingzh/add_support_spv_intel_predicated_io/llvm-project/build/bin/llc+0xbbc425)
>From 927ed634079a96f173b097c4afe9b508cda84416 Mon Sep 17 00:00:00 2001
From: "Zhang, Yixing" <yixing.zhang at intel.com>
Date: Sat, 4 Oct 2025 20:05:50 -0700
Subject: [PATCH 5/9] modify how we lower the builtin
---
.../SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp | 9 ++++++
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 32 ++++++++-----------
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 6 ++--
.../predicated_io_generic.ll | 9 +++---
4 files changed, 29 insertions(+), 27 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
index 776208bd3e693..4a44e057890f8 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
@@ -284,6 +284,15 @@ void SPIRVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
}
break;
}
+ case SPIRV::OpPredicatedLoadINTEL: {
+ const unsigned NumOps = MI->getNumOperands();
+ if (NumOps > NumFixedOps) {
+ OS << ' ';
+ printSymbolicOperand<OperandCategory::MemoryOperandOperand>(
+ MI, FirstVariableIndex, OS);
+ break;
+ }
+ }
default:
printRemainingVariableOps(MI, NumFixedOps, OS);
break;
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 7d72317409197..6aa36bb7e5d09 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -1131,24 +1131,6 @@ static bool buildPipeInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
}
}
-// Helper function for building Intel's predicated load/store instructions.
-static bool buildPredicatedLoadStoreInst(const SPIRV::IncomingCall *Call,
- unsigned Opcode,
- MachineIRBuilder &MIRBuilder,
- SPIRVGlobalRegistry *GR) {
- // Generate SPIRV instruction accordingly.
- if (Call->isSpirvOp())
- return buildOpFromWrapper(MIRBuilder, Opcode, Call, Register(0));
-
- auto MIB = MIRBuilder.buildInstr(Opcode)
- .addDef(Call->ReturnRegister)
- .addUse(GR->getSPIRVTypeID(Call->ReturnType));
- for (unsigned i = 0; i < Call->Arguments.size(); ++i)
- MIB.addUse(Call->Arguments[i]);
-
- return true;
-}
-
static unsigned getNumComponentsForDim(SPIRV::Dim::Dim dim) {
switch (dim) {
case SPIRV::Dim::DIM_1D:
@@ -2444,7 +2426,19 @@ static bool generatePredicatedLoadStoreInst(const SPIRV::IncomingCall *Call,
unsigned Opcode =
SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode;
- return buildPredicatedLoadStoreInst(Call, Opcode, MIRBuilder, GR);
+ bool IsSet = Opcode != SPIRV::OpPredicatedStoreINTEL;
+ unsigned ArgSz = Call->Arguments.size();
+ unsigned LiteralIdx = 0;
+ if(ArgSz > 3) {
+ LiteralIdx = 3;
+ }
+ SmallVector<uint32_t, 1> ImmArgs;
+ MachineRegisterInfo *MRI = MIRBuilder.getMRI();
+ if (LiteralIdx > 0)
+ ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[LiteralIdx], MRI));
+ Register TypeReg = GR->getSPIRVTypeID(Call->ReturnType);
+ return buildOpFromWrapper(MIRBuilder, Opcode, Call,
+ IsSet ? TypeReg : Register(0), ImmArgs);
}
static bool buildNDRange(const SPIRV::IncomingCall *Call,
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 2304db952f0de..a61351eba03f8 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -989,7 +989,7 @@ def OpSubgroup2DBlockStoreINTEL: Op<6235, (outs), (ins ID:$element_size, ID:$blo
"OpSubgroup2DBlockStoreINTEL $element_size $block_width $block_height $block_count $src_ptr $dst_base_ptr $memory_width $memory_height $memory_pitch $coord">;
// SPV_INTEL_predicated_io
-def OpPredicatedLoadINTEL: Op<6528, (outs ID:$res), (ins ID:$ptr, ID:$predicate, ID:$default_value),
- "$res = OpPredicatedLoadINTEL $ptr $predicate $default_value">;
-def OpPredicatedStoreINTEL: Op<6529, (outs), (ins ID:$ptr, ID:$object, ID:$predicate),
+def OpPredicatedLoadINTEL: Op<6528, (outs ID:$res), (ins TYPE:$resType, ID:$ptr, ID:$predicate, ID:$default_value, variable_ops),
+ "$res = OpPredicatedLoadINTEL $resType $ptr $predicate $default_value">;
+def OpPredicatedStoreINTEL: Op<6529, (outs), (ins ID:$ptr, ID:$object, ID:$predicate, variable_ops),
"OpPredicatedStoreINTEL $ptr $object $predicate">;
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll
index f176903860e31..8f15de00bbec5 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll
@@ -9,7 +9,6 @@
; CHECK-DAG: Extension "SPV_INTEL_predicated_io"
; CHECK-DAG: %[[Int32Ty:[0-9]+]] = OpTypeInt 32 0
-; CHECK-DAG: %[[Const0:[0-9]+]] = OpConstant %[[Int32Ty]] 0
; CHECK-DAG: %[[VoidTy:[0-9]+]] = OpTypeVoid
; CHECK-DAG: %[[IntPtrTy:[0-9]+]] = OpTypePointer CrossWorkgroup %[[Int32Ty]]
; CHECK-DAG: %[[BoolTy:[0-9]+]] = OpTypeBool
@@ -18,10 +17,10 @@
; CHECK: %[[DefaultVal:]] = FunctionParameter %[[Int32Ty]]
; CHECK: %[[StoreObj:]] = FunctionParameter %[[Int32Ty]]
; CHECK: %[[Predicate:]] = FunctionParameter %[[BoolTy]]
-; CHECK: PredicatedLoadINTEL %[[Int32Ty]] %[[Result1:]] %[[LoadPtr]] %[[Predicate]] %[[DefaultVal]]
-; CHECK: PredicatedLoadINTEL %[[Int32Ty]] %[[Result2:]] %[[LoadPtr]] %[[Predicate]] %[[DefaultVal]] %[[Const0]]
+; CHECK: PredicatedLoadINTEL %[[Int32Ty]] %[[LoadPtr]] %[[Predicate]] %[[DefaultVal]]
+; CHECK: PredicatedLoadINTEL %[[Int32Ty]] %[[LoadPtr]] %[[Predicate]] %[[DefaultVal]] 0
; CHECK: PredicatedStoreINTEL %[[StorePtr]] %[[StoreObj]] %[[Predicate]]
-; CHECK: PredicatedStoreINTEL %[[StorePtr]] %[[StoreObj]] %[[Predicate]] %[[Const0]]
+; CHECK: PredicatedStoreINTEL %[[StorePtr]] %[[StoreObj]] %[[Predicate]] 0
define spir_func void @foo(ptr addrspace(1) %load_pointer, ptr addrspace(1) %store_pointer, i32 %default_value, i32 %store_object, i1 zeroext %predicate) {
entry:
@@ -35,4 +34,4 @@ entry:
declare spir_func i32 @_Z27__spirv_PredicatedLoadINTELPU3AS1Kibi(ptr addrspace(1), i1, i32)
declare spir_func i32 @_Z27__spirv_PredicatedLoadINTELPU3AS1Kibii(ptr addrspace(1), i1, i32, i32)
declare spir_func void @_Z28__spirv_PredicatedStoreINTELPU3AS1Kiib(ptr addrspace(1), i32, i1)
-declare spir_func void @_Z28__spirv_PredicatedStoreINTELPU3AS1Kiibi(ptr addrspace(1), i32, i1, i32)
+declare spir_func void @_Z28__spirv_PredicatedStoreINTELPU3AS1Kiibi(ptr addrspace(1), i32, i1, i32)
\ No newline at end of file
>From 3c7dc4ed5607f21e97fd481013d35e54fd40bda3 Mon Sep 17 00:00:00 2001
From: "Zhang, Yixing" <yixing.zhang at intel.com>
Date: Sun, 5 Oct 2025 09:41:19 -0700
Subject: [PATCH 6/9] fix issue with the test
---
.../SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp | 6 ++++--
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 1 +
.../predicated_io_generic.ll | 18 +++++++++---------
3 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
index 4a44e057890f8..df082d5f80aa8 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
@@ -284,14 +284,16 @@ void SPIRVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
}
break;
}
- case SPIRV::OpPredicatedLoadINTEL: {
+ case SPIRV::OpPredicatedLoadINTEL:
+ case SPIRV::OpPredicatedStoreINTEL: {
const unsigned NumOps = MI->getNumOperands();
if (NumOps > NumFixedOps) {
OS << ' ';
printSymbolicOperand<OperandCategory::MemoryOperandOperand>(
- MI, FirstVariableIndex, OS);
+ MI, NumOps - 1, OS);
break;
}
+ break;
}
default:
printRemainingVariableOps(MI, NumFixedOps, OS);
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 6aa36bb7e5d09..5bad2f99b97a9 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -2432,6 +2432,7 @@ static bool generatePredicatedLoadStoreInst(const SPIRV::IncomingCall *Call,
if(ArgSz > 3) {
LiteralIdx = 3;
}
+
SmallVector<uint32_t, 1> ImmArgs;
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
if (LiteralIdx > 0)
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll
index 8f15de00bbec5..123249007bddf 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll
@@ -9,18 +9,18 @@
; CHECK-DAG: Extension "SPV_INTEL_predicated_io"
; CHECK-DAG: %[[Int32Ty:[0-9]+]] = OpTypeInt 32 0
-; CHECK-DAG: %[[VoidTy:[0-9]+]] = OpTypeVoid
; CHECK-DAG: %[[IntPtrTy:[0-9]+]] = OpTypePointer CrossWorkgroup %[[Int32Ty]]
; CHECK-DAG: %[[BoolTy:[0-9]+]] = OpTypeBool
-; CHECK: %[[LoadPtr:]] = FunctionParameter %[[IntPtrTy]]
-; CHECK: %[[StorePtr:]] = FunctionParameter %[[IntPtrTy]]
-; CHECK: %[[DefaultVal:]] = FunctionParameter %[[Int32Ty]]
-; CHECK: %[[StoreObj:]] = FunctionParameter %[[Int32Ty]]
-; CHECK: %[[Predicate:]] = FunctionParameter %[[BoolTy]]
+; CHECK-DAG: %[[VoidTy:[0-9]+]] = OpTypeVoid
+; CHECK: %[[LoadPtr:[0-9]+]] = OpFunctionParameter %[[IntPtrTy]]
+; CHECK: %[[StorePtr:[0-9]+]] = OpFunctionParameter %[[IntPtrTy]]
+; CHECK: %[[DefaultVal:[0-9]+]] = OpFunctionParameter %[[Int32Ty]]
+; CHECK: %[[StoreObj:[0-9]+]] = OpFunctionParameter %[[Int32Ty]]
+; CHECK: %[[Predicate:[0-9]+]] = OpFunctionParameter %[[BoolTy]]
; CHECK: PredicatedLoadINTEL %[[Int32Ty]] %[[LoadPtr]] %[[Predicate]] %[[DefaultVal]]
-; CHECK: PredicatedLoadINTEL %[[Int32Ty]] %[[LoadPtr]] %[[Predicate]] %[[DefaultVal]] 0
+; CHECK: PredicatedLoadINTEL %[[Int32Ty]] %[[LoadPtr]] %[[Predicate]] %[[DefaultVal]] None
; CHECK: PredicatedStoreINTEL %[[StorePtr]] %[[StoreObj]] %[[Predicate]]
-; CHECK: PredicatedStoreINTEL %[[StorePtr]] %[[StoreObj]] %[[Predicate]] 0
+; CHECK: PredicatedStoreINTEL %[[StorePtr]] %[[StoreObj]] %[[Predicate]] None
define spir_func void @foo(ptr addrspace(1) %load_pointer, ptr addrspace(1) %store_pointer, i32 %default_value, i32 %store_object, i1 zeroext %predicate) {
entry:
@@ -34,4 +34,4 @@ entry:
declare spir_func i32 @_Z27__spirv_PredicatedLoadINTELPU3AS1Kibi(ptr addrspace(1), i1, i32)
declare spir_func i32 @_Z27__spirv_PredicatedLoadINTELPU3AS1Kibii(ptr addrspace(1), i1, i32, i32)
declare spir_func void @_Z28__spirv_PredicatedStoreINTELPU3AS1Kiib(ptr addrspace(1), i32, i1)
-declare spir_func void @_Z28__spirv_PredicatedStoreINTELPU3AS1Kiibi(ptr addrspace(1), i32, i1, i32)
\ No newline at end of file
+declare spir_func void @_Z28__spirv_PredicatedStoreINTELPU3AS1Kiibi(ptr addrspace(1), i32, i1, i32)
>From e1c0cb818384ba38d8d765bb95c9f74131995cb8 Mon Sep 17 00:00:00 2001
From: "Zhang, Yixing" <yixing.zhang at intel.com>
Date: Sun, 5 Oct 2025 09:48:43 -0700
Subject: [PATCH 7/9] code clean up
---
llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp | 2 +-
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 6 +++---
llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp | 3 ++-
3 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
index df082d5f80aa8..35a2ee16b2309 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
@@ -290,7 +290,7 @@ void SPIRVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
if (NumOps > NumFixedOps) {
OS << ' ';
printSymbolicOperand<OperandCategory::MemoryOperandOperand>(
- MI, NumOps - 1, OS);
+ MI, NumOps - 1, OS);
break;
}
break;
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 5bad2f99b97a9..5202c39843f4c 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -2419,7 +2419,7 @@ static bool generatePipeInst(const SPIRV::IncomingCall *Call,
return buildPipeInst(Call, Opcode, Scope, MIRBuilder, GR);
}
-static bool generatePredicatedLoadStoreInst(const SPIRV::IncomingCall *Call,
+static bool generatePredicatedLoadStoreInst(const SPIRV::IncomingCall *Call,
MachineIRBuilder &MIRBuilder,
SPIRVGlobalRegistry *GR) {
const SPIRV::DemangledBuiltin *Builtin = Call->Builtin;
@@ -2429,14 +2429,14 @@ static bool generatePredicatedLoadStoreInst(const SPIRV::IncomingCall *Call,
bool IsSet = Opcode != SPIRV::OpPredicatedStoreINTEL;
unsigned ArgSz = Call->Arguments.size();
unsigned LiteralIdx = 0;
- if(ArgSz > 3) {
+ if (ArgSz > 3) {
LiteralIdx = 3;
}
SmallVector<uint32_t, 1> ImmArgs;
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
if (LiteralIdx > 0)
- ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[LiteralIdx], MRI));
+ ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[LiteralIdx], MRI));
Register TypeReg = GR->getSPIRVTypeID(Call->ReturnType);
return buildOpFromWrapper(MIRBuilder, Opcode, Call,
IsSet ? TypeReg : Register(0), ImmArgs);
diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
index 60bf001fe933c..5f3ed862af893 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
@@ -152,7 +152,8 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
{"SPV_EXT_relaxed_printf_string_address_space",
SPIRV::Extension::Extension::
SPV_EXT_relaxed_printf_string_address_space},
- {"SPV_INTEL_predicated_io", SPIRV::Extension::Extension::SPV_INTEL_predicated_io}};
+ {"SPV_INTEL_predicated_io",
+ SPIRV::Extension::Extension::SPV_INTEL_predicated_io}};
bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
StringRef ArgValue,
>From 961a5e9ba5daf5c92f979e3e61b9366013915477 Mon Sep 17 00:00:00 2001
From: "Zhang, Yixing" <yixing.zhang at intel.com>
Date: Mon, 6 Oct 2025 05:40:38 -0700
Subject: [PATCH 8/9] remove the spirv-val check because the capacity is not
enable in spirv header yet
---
.../extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll
index 123249007bddf..a3127e80772aa 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll
@@ -1,6 +1,5 @@
; RUN: not llc -O0 -mtriple=spirv64-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_predicated_io %s -o - | FileCheck %s
-; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s --spirv-ext=+SPV_INTEL_predicated_io -o - -filetype=obj | spirv-val %}
; CHECK-ERROR: LLVM ERROR: OpPredicated[Load/Store]INTEL
; CHECK-ERROR-SAME: instructions require the following SPIR-V extension: SPV_INTEL_predicated_io
>From d9056e06b514bd994ebd53a6c5d8f6515815b404 Mon Sep 17 00:00:00 2001
From: "Zhang, Yixing" <yixing.zhang at intel.com>
Date: Tue, 7 Oct 2025 07:55:13 -0700
Subject: [PATCH 9/9] make change based on the comment
---
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 5202c39843f4c..ccb68f269e4f3 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -2428,15 +2428,12 @@ static bool generatePredicatedLoadStoreInst(const SPIRV::IncomingCall *Call,
bool IsSet = Opcode != SPIRV::OpPredicatedStoreINTEL;
unsigned ArgSz = Call->Arguments.size();
- unsigned LiteralIdx = 0;
- if (ArgSz > 3) {
- LiteralIdx = 3;
- }
-
SmallVector<uint32_t, 1> ImmArgs;
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
- if (LiteralIdx > 0)
- ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[LiteralIdx], MRI));
+ // Memory operand is optional and is literal.
+ if (ArgSz > 3)
+ ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[/*Literal index*/ 3], MRI));
+
Register TypeReg = GR->getSPIRVTypeID(Call->ReturnType);
return buildOpFromWrapper(MIRBuilder, Opcode, Call,
IsSet ? TypeReg : Register(0), ImmArgs);
More information about the llvm-commits
mailing list