[llvm] 3751c83 - [RISCV] Simplify RUN lines in float-imm.ll and half-imm.ll. NFC.
Jim Lin via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 6 23:51:00 PDT 2025
Author: Jim Lin
Date: 2025-10-07T14:50:31+08:00
New Revision: 3751c8341583c5522df6f227fc7b7eb8a049b483
URL: https://github.com/llvm/llvm-project/commit/3751c8341583c5522df6f227fc7b7eb8a049b483
DIFF: https://github.com/llvm/llvm-project/commit/3751c8341583c5522df6f227fc7b7eb8a049b483.diff
LOG: [RISCV] Simplify RUN lines in float-imm.ll and half-imm.ll. NFC.
Added:
Modified:
llvm/test/CodeGen/RISCV/float-imm.ll
llvm/test/CodeGen/RISCV/half-imm.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/float-imm.ll b/llvm/test/CodeGen/RISCV/float-imm.ll
index a1737325d8aa5..610c72b5f932e 100644
--- a/llvm/test/CodeGen/RISCV/float-imm.ll
+++ b/llvm/test/CodeGen/RISCV/float-imm.ll
@@ -4,9 +4,9 @@
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: -target-abi=lp64f | FileCheck %s
; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
-; RUN: -target-abi=ilp32 | FileCheck --check-prefixes=CHECKZFINX,RV32ZFINX %s
+; RUN: -target-abi=ilp32 | FileCheck --check-prefixes=CHECKZFINX %s
; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
-; RUN: -target-abi=lp64 | FileCheck --check-prefixes=CHECKZFINX,RV64ZFINX %s
+; RUN: -target-abi=lp64 | FileCheck --check-prefixes=CHECKZFINX %s
define float @float_imm() nounwind {
; CHECK-LABEL: float_imm:
@@ -68,6 +68,3 @@ define float @float_negative_zero(ptr %pf) nounwind {
; CHECKZFINX-NEXT: ret
ret float -0.0
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; RV32ZFINX: {{.*}}
-; RV64ZFINX: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/half-imm.ll b/llvm/test/CodeGen/RISCV/half-imm.ll
index fc2c017d1c400..ec1a7a4dfc4f0 100644
--- a/llvm/test/CodeGen/RISCV/half-imm.ll
+++ b/llvm/test/CodeGen/RISCV/half-imm.ll
@@ -5,20 +5,20 @@
; RUN: -target-abi lp64f < %s | FileCheck %s
; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
; RUN: -target-abi ilp32 < %s \
-; RUN: | FileCheck -check-prefix=RV32IZHINX %s
+; RUN: | FileCheck -check-prefixes=CHECKIZHINX %s
; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
; RUN: -target-abi lp64 < %s \
-; RUN: | FileCheck -check-prefix=RV64IZHINX %s
+; RUN: | FileCheck -check-prefixes=CHECKIZHINX %s
; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
; RUN: -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
; RUN: -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
; RUN: -target-abi ilp32 < %s \
-; RUN: | FileCheck -check-prefixes=CHECKIZHINXMIN,RV32IZHINXMIN %s
+; RUN: | FileCheck -check-prefixes=CHECKIZHINXMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
; RUN: -target-abi lp64 < %s \
-; RUN: | FileCheck -check-prefixes=CHECKIZHINXMIN,RV64IZHINXMIN %s
+; RUN: | FileCheck -check-prefixes=CHECKIZHINXMIN %s
define half @half_imm() nounwind {
; CHECK-LABEL: half_imm:
@@ -28,19 +28,12 @@ define half @half_imm() nounwind {
; CHECK-NEXT: fmv.h.x fa0, a0
; CHECK-NEXT: ret
;
-; RV32IZHINX-LABEL: half_imm:
-; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a0, 4
-; RV32IZHINX-NEXT: addi a0, a0, 512
-; RV32IZHINX-NEXT: # kill: def $x10_h killed $x10_h killed $x10
-; RV32IZHINX-NEXT: ret
-;
-; RV64IZHINX-LABEL: half_imm:
-; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a0, 4
-; RV64IZHINX-NEXT: addi a0, a0, 512
-; RV64IZHINX-NEXT: # kill: def $x10_h killed $x10_h killed $x10
-; RV64IZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: half_imm:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: lui a0, 4
+; CHECKIZHINX-NEXT: addi a0, a0, 512
+; CHECKIZHINX-NEXT: # kill: def $x10_h killed $x10_h killed $x10
+; CHECKIZHINX-NEXT: ret
;
; CHECKIZFHMIN-LABEL: half_imm:
; CHECKIZFHMIN: # %bb.0:
@@ -67,19 +60,12 @@ define half @half_imm_op(half %a) nounwind {
; CHECK-NEXT: fadd.h fa0, fa0, fa5
; CHECK-NEXT: ret
;
-; RV32IZHINX-LABEL: half_imm_op:
-; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: li a1, 15
-; RV32IZHINX-NEXT: slli a1, a1, 10
-; RV32IZHINX-NEXT: fadd.h a0, a0, a1
-; RV32IZHINX-NEXT: ret
-;
-; RV64IZHINX-LABEL: half_imm_op:
-; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: li a1, 15
-; RV64IZHINX-NEXT: slli a1, a1, 10
-; RV64IZHINX-NEXT: fadd.h a0, a0, a1
-; RV64IZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: half_imm_op:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: li a1, 15
+; CHECKIZHINX-NEXT: slli a1, a1, 10
+; CHECKIZHINX-NEXT: fadd.h a0, a0, a1
+; CHECKIZHINX-NEXT: ret
;
; CHECKIZFHMIN-LABEL: half_imm_op:
; CHECKIZFHMIN: # %bb.0:
@@ -107,15 +93,10 @@ define half @half_positive_zero(ptr %pf) nounwind {
; CHECK-NEXT: fmv.h.x fa0, zero
; CHECK-NEXT: ret
;
-; RV32IZHINX-LABEL: half_positive_zero:
-; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: li a0, 0
-; RV32IZHINX-NEXT: ret
-;
-; RV64IZHINX-LABEL: half_positive_zero:
-; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: li a0, 0
-; RV64IZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: half_positive_zero:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: li a0, 0
+; CHECKIZHINX-NEXT: ret
;
; CHECKIZFHMIN-LABEL: half_positive_zero:
; CHECKIZFHMIN: # %bb.0:
@@ -136,15 +117,10 @@ define half @half_negative_zero(ptr %pf) nounwind {
; CHECK-NEXT: fmv.h.x fa0, a0
; CHECK-NEXT: ret
;
-; RV32IZHINX-LABEL: half_negative_zero:
-; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a0, 1048568
-; RV32IZHINX-NEXT: ret
-;
-; RV64IZHINX-LABEL: half_negative_zero:
-; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a0, 1048568
-; RV64IZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: half_negative_zero:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: lui a0, 1048568
+; CHECKIZHINX-NEXT: ret
;
; CHECKIZFHMIN-LABEL: half_negative_zero:
; CHECKIZFHMIN: # %bb.0:
@@ -158,6 +134,3 @@ define half @half_negative_zero(ptr %pf) nounwind {
; CHECKIZHINXMIN-NEXT: ret
ret half -0.0
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; RV32IZHINXMIN: {{.*}}
-; RV64IZHINXMIN: {{.*}}
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