[llvm] [ASan][RISCV] Support asan check for segment load/store RVV intrinsics. (PR #161317)

[Florian Mayer via llvm-commits]

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@@ -2747,20 +2747,68 @@ bool RISCVTTIImpl::getTgtMemIntrinsic(IntrinsicInst *Inst,
   Intrinsic::ID IID = Inst->getIntrinsicID();
   LLVMContext &C = Inst->getContext();
   bool HasMask = false;
+
+  auto getSegNum = [](const IntrinsicInst *II, unsigned PtrOperandNo,
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fmayer wrote:

maybe just make this a `static` function'? this doesn't need to be inline

https://github.com/llvm/llvm-project/pull/161317