[llvm] [RISCV][GISel] Support Zalasr (PR #161774)

[Sam Elliott via llvm-commits]

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@@ -156,6 +165,26 @@ define i8 @atomic_load_i8_acquire(ptr %a) nounwind {
 ; RV64IA-TSO-TRAILING-FENCE:       # %bb.0:
 ; RV64IA-TSO-TRAILING-FENCE-NEXT:    lbu a0, 0(a0)
 ; RV64IA-TSO-TRAILING-FENCE-NEXT:    ret
+;
+; RV32IA-ZALASR-WMO-LABEL: atomic_load_i8_acquire:
+; RV32IA-ZALASR-WMO:       # %bb.0:
+; RV32IA-ZALASR-WMO-NEXT:    lb.aq a0, (a0)
+; RV32IA-ZALASR-WMO-NEXT:    ret
+;
+; RV32IA-ZALASR-TSO-LABEL: atomic_load_i8_acquire:
+; RV32IA-ZALASR-TSO:       # %bb.0:
+; RV32IA-ZALASR-TSO-NEXT:    lbu a0, 0(a0)
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lenary wrote:

Not a blocker: One minor difference between these cases and the equivalent SDag cases, is that these use `lbu a0, 0(a0)` rather than `lb a0, 0(a0)`, even after your patch to change this with GISel on Oct 1st (129d5ce14c4fd094799b50e6ebe6c8f9ca5003f1). I think the GISel codegen (as here) is the preferred codegen though.

https://github.com/llvm/llvm-project/pull/161774