[llvm] [BranchRelaxation] Fix invalid branch generation in branch-relaxation (PR #162065)
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Mon Oct 6 09:59:41 PDT 2025
https://github.com/sc-clulzze updated https://github.com/llvm/llvm-project/pull/162065
>From 33b74f5d6bef49667f37ef6b41605eb34dd072f2 Mon Sep 17 00:00:00 2001
From: sc-cluzze <d.marakulin at syntacore.com>
Date: Fri, 3 Oct 2025 10:28:48 +0000
Subject: [PATCH 1/2] [BranchRelaxation] Fix invalid branch generation in
branch-relaxation
---
llvm/lib/CodeGen/BranchRelaxation.cpp | 14 ++++++++++++++
llvm/test/CodeGen/RISCV/branch-rel.mir | 24 ++++++++++++++++++++++++
2 files changed, 38 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/branch-rel.mir
diff --git a/llvm/lib/CodeGen/BranchRelaxation.cpp b/llvm/lib/CodeGen/BranchRelaxation.cpp
index 2d50167faa085..bb75c638d1bcc 100644
--- a/llvm/lib/CodeGen/BranchRelaxation.cpp
+++ b/llvm/lib/CodeGen/BranchRelaxation.cpp
@@ -491,6 +491,20 @@ bool BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) {
return true;
}
if (FBB) {
+ // If we get here with a MBB which ends like this:
+ //
+ // bb.1:
+ // successors: %bb.2;
+ // ...
+ // BNE $x1, $x0, %bb.2
+ // PseudoBR %bb.2
+ //
+ // Just remove conditional branch.
+ if (TBB == FBB) {
+ BlockInfo[MBB->getNumber()].Size -= TII->getInstSizeInBytes(MI);
+ MI.eraseFromParent();
+ return true;
+ }
// We need to split the basic block here to obtain two long-range
// unconditional branches.
NewBB = createNewBlockAfter(*MBB);
diff --git a/llvm/test/CodeGen/RISCV/branch-rel.mir b/llvm/test/CodeGen/RISCV/branch-rel.mir
new file mode 100644
index 0000000000000..218ebe1d09f44
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/branch-rel.mir
@@ -0,0 +1,24 @@
+# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+# RUN: llc %s -mtriple=riscv64 -run-pass=branch-relaxation -o - -verify-machineinstrs | FileCheck %s
+
+--- |
+ define void @foo() {
+ ret void
+ }
+...
+---
+name: foo
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x1
+ BNE $x1, $x0, %bb.3
+ PseudoBR %bb.3
+ bb.1:
+ liveins: $x1
+ INLINEASM &".space 4096", 1
+ BGE $x1, $x0, %bb.3
+ bb.3:
+ PseudoRET
+## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+# CHECK: {{.*}}
>From fd7036eca91029c020997f949c16a69cd56450fb Mon Sep 17 00:00:00 2001
From: sc-cluzze <d.marakulin at syntacore.com>
Date: Mon, 6 Oct 2025 16:57:57 +0000
Subject: [PATCH 2/2] Generate test checks correctly
---
llvm/test/CodeGen/RISCV/branch-rel.mir | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/branch-rel.mir b/llvm/test/CodeGen/RISCV/branch-rel.mir
index 218ebe1d09f44..1ed5f5715a825 100644
--- a/llvm/test/CodeGen/RISCV/branch-rel.mir
+++ b/llvm/test/CodeGen/RISCV/branch-rel.mir
@@ -1,4 +1,4 @@
-# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc %s -mtriple=riscv64 -run-pass=branch-relaxation -o - -verify-machineinstrs | FileCheck %s
--- |
@@ -10,6 +10,22 @@
name: foo
tracksRegLiveness: true
body: |
+ ; CHECK-LABEL: name: foo
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: liveins: $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: PseudoBR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: liveins: $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: INLINEASM &".space 4096", 1 /* sideeffect attdialect */
+ ; CHECK-NEXT: BGE $x1, $x0, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: PseudoRET
bb.0:
liveins: $x1
BNE $x1, $x0, %bb.3
@@ -21,4 +37,3 @@ body: |
bb.3:
PseudoRET
## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-# CHECK: {{.*}}
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