[llvm] [AMDGPU] siloadstoreopt generate REG_SEQUENCE with aligned operands (PR #162088)

[Matt Arsenault via llvm-commits]

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@@ -1363,6 +1363,15 @@ SILoadStoreOptimizer::checkAndPrepareMerge(CombineInfo &CI,
   return Where;
 }
 
+static bool isCompatibleAlignSubReg(const TargetRegisterClass *RC, unsigned Idx,
+                                    const GCNSubtarget *STM,
+                                    const SIRegisterInfo *TRI) {
+  if (!STM->needsAlignedVGPRs() || !TRI->isVGPRClass(RC) ||
+      !TRI->isProperlyAlignedRC(*RC) || AMDGPU::getRegBitWidth(*RC) == 32)
+    return true;
+  return !(TRI->getChannelFromSubReg(Idx) & 0x1);
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arsenm wrote:

You should use none of the functions here; not needsAlignedVGPRs, not isProperlyAlignedRC, and probably not getChannelFromSubReg or getRegBitWidth either. 

You either want RC->hasSubClassEq() or TRI->getCommonSubClass depending on the context. 

In this case it looks like getTargetRegisterClass isn't returning the correct class to use

https://github.com/llvm/llvm-project/pull/162088