[llvm] 1cc9a8c - AMDGPU: Stop using the wavemask register class for SCC cross class copies (#161801)

[via llvm-commits]

Author: Matt Arsenault
Date: 2025-10-07T00:44:45+09:00
New Revision: 1cc9a8c1272f428edcd4caf871cb66f973f4c13e

URL: https://github.com/llvm/llvm-project/commit/1cc9a8c1272f428edcd4caf871cb66f973f4c13e
DIFF: https://github.com/llvm/llvm-project/commit/1cc9a8c1272f428edcd4caf871cb66f973f4c13e.diff

LOG: AMDGPU: Stop using the wavemask register class for SCC cross class copies (#161801)

SCC should be copied to a 32-bit SGPR. Using a wave mask doesn't make
sense.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index bd95ee4042874..311557909916a 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1118,9 +1118,7 @@ SIRegisterInfo::getPointerRegClass(unsigned Kind) const {
 
 const TargetRegisterClass *
 SIRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
-  if (RC == &AMDGPU::SCC_CLASSRegClass)
-    return getWaveMaskRegClass();
-  return RC;
+  return RC == &AMDGPU::SCC_CLASSRegClass ? &AMDGPU::SReg_32RegClass : RC;
 }
 
 static unsigned getNumSubRegsForSpillOp(const MachineInstr &MI,