[llvm] [X86][GISel] Add missing legalization for G_IMPLICIT_DEF (PR #161699)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 6 01:37:35 PDT 2025
https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/161699
>From 81e18b2c8710c299e5d5fb3fc99d435a5d8006f0 Mon Sep 17 00:00:00 2001
From: bonsthie <barnabe.bonnet at gmail.com>
Date: Thu, 2 Oct 2025 16:25:50 +0200
Subject: [PATCH 1/4] [X86][GISel] Add missing legalization for G_IMPLICIT_DEF
Legalize scalar and vector integer types for G_IMPLICIT_DEF at SSE2/AVX2/AVX-512 widths.
This is groundwork for upcoming G_*_VECTOR legalization, since vector inserts/builds rely on undef bases.
---
.../lib/Target/X86/GISel/X86LegalizerInfo.cpp | 22 ++++++++++++-
.../GlobalISel/legalize-g_implicit_def.mir | 32 +++++++++++++++++++
2 files changed, 53 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/X86/GlobalISel/legalize-g_implicit_def.mir
diff --git a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
index 143c4c43e611a..d16dda91cc495 100644
--- a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
+++ b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
@@ -91,7 +91,27 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
// s128 = EXTEND (G_IMPLICIT_DEF s32/s64) -> s128 = G_IMPLICIT_DEF
getActionDefinitionsBuilder(G_IMPLICIT_DEF)
.legalFor({p0, s1, s8, s16, s32, s64})
- .legalFor(Is64Bit, {s128});
+ .legalFor(Is64Bit, {s128})
+ .legalFor(HasSSE2, {v16s8, v8s16, v4s32, v2s64})
+ .legalFor(HasAVX, {v8s32, v4s64})
+ .legalFor(HasAVX2, {v32s8, v16s16, v8s32, v4s64})
+ .legalFor(HasAVX512, {v16s32, v8s64})
+ .legalFor(HasBWI, {v64s8, v32s16})
+ .widenScalarOrEltToNextPow2(0, /*Min=*/8)
+ .clampScalarOrElt(0, s8, sMaxScalar)
+ .moreElementsToNextPow2(0)
+ .clampMinNumElements(0, s8, 16)
+ .clampMinNumElements(0, s16, 8)
+ .clampMinNumElements(0, s32, 4)
+ .clampMinNumElements(0, s64, 2)
+ .clampMaxNumElements(0, s8, HasBWI ? 64 : (HasAVX2 ? 32 : 16))
+ .clampMaxNumElements(0, s16, HasBWI ? 32 : (HasAVX2 ? 16 : 8))
+ .clampMaxNumElements(0, s32, HasAVX512 ? 16 : (HasAVX2 ? 8 : 4))
+ .clampMaxNumElements(0, s64, HasAVX512 ? 8 : (HasAVX2 ? 4 : 2))
+ .clampMaxNumElements(0, p0,
+ Is64Bit ? s64MaxVector.getNumElements()
+ : s32MaxVector.getNumElements())
+ .scalarizeIf(scalarOrEltWiderThan(0, 64), 0);
getActionDefinitionsBuilder(G_CONSTANT)
.legalFor({p0, s8, s16, s32})
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-g_implicit_def.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-g_implicit_def.mir
new file mode 100644
index 0000000000000..b02832b9824ad
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-g_implicit_def.mir
@@ -0,0 +1,32 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=avx2 -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o - | FileCheck %s --check-prefixes=CHECK,AVX2
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=sse2 -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o - | FileCheck %s --check-prefixes=CHECK,SSE2
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=avx512f -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o - | FileCheck %s --check-prefixes=CHECK,AVX512F
+
+
+---
+name: test_basic_g_implicit_def_v8i64
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_basic_g_implicit_def_v8i64
+ ; AVX512F: {{%[0-9]+}}:_(<8 x s64>) = G_IMPLICIT_DEF
+ ; AVX2: [[DEF_AVX2:%[0-9]+]]:_(<4 x s64>) = G_IMPLICIT_DEF
+ ; AVX2-NEXT: {{%[0-9]+}}:_(<8 x s64>) = G_CONCAT_VECTORS [[DEF_AVX2]](<4 x s64>), [[DEF_AVX2]](<4 x s64>)
+ ; SSE2: [[DEF_SSE2:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
+ ; SSE2-NEXT: {{%[0-9]+}}:_(<8 x s64>) = G_CONCAT_VECTORS [[DEF_SSE2]](<2 x s64>), [[DEF_SSE2]](<2 x s64>), [[DEF_SSE2]](<2 x s64>), [[DEF_SSE2]](<2 x s64>)
+ %0:_(<8 x s64>) = G_IMPLICIT_DEF
+ RET 0, implicit %0
+...
+
+---
+name: test_g_implicit_def_cample_size
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: test_g_implicit_def_cample_size
+ ; AVX512: {{%[0-9]+}}:_(<8 x s64>) = G_IMPLICIT_DEF
+ ; AVX2: {{%[0-9]+}}:_(<4 x s64>) = G_IMPLICIT_DEF
+ ; SSE2: {{%[0-9]+}}:_(<2 x s64>) = G_IMPLICIT_DEF
+ %0:_(<5 x s63>) = G_IMPLICIT_DEF
+ RET 0, implicit %0
+...
+
+
>From 00247707abbc91d4920ca410c89e4679e33b44d5 Mon Sep 17 00:00:00 2001
From: bonsthie <barnabe.bonnet at gmail.com>
Date: Fri, 3 Oct 2025 12:55:30 +0200
Subject: [PATCH 2/4] [X86][GISel] Unify AVX/AVX2 and AVX512/AVX512BW type
legality
Merge AVX2 types into AVX and AVX512BW types into AVX512, since the vector
types are valid in both cases.
---
llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
index d16dda91cc495..b7da9609e962e 100644
--- a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
+++ b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
@@ -93,10 +93,8 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
.legalFor({p0, s1, s8, s16, s32, s64})
.legalFor(Is64Bit, {s128})
.legalFor(HasSSE2, {v16s8, v8s16, v4s32, v2s64})
- .legalFor(HasAVX, {v8s32, v4s64})
- .legalFor(HasAVX2, {v32s8, v16s16, v8s32, v4s64})
- .legalFor(HasAVX512, {v16s32, v8s64})
- .legalFor(HasBWI, {v64s8, v32s16})
+ .legalFor(HasAVX, {v32s8, v16s16, v8s32, v4s64})
+ .legalFor(HasAVX512, {v64s8, v32s16, v16s32, v8s64})
.widenScalarOrEltToNextPow2(0, /*Min=*/8)
.clampScalarOrElt(0, s8, sMaxScalar)
.moreElementsToNextPow2(0)
@@ -104,10 +102,10 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
.clampMinNumElements(0, s16, 8)
.clampMinNumElements(0, s32, 4)
.clampMinNumElements(0, s64, 2)
- .clampMaxNumElements(0, s8, HasBWI ? 64 : (HasAVX2 ? 32 : 16))
- .clampMaxNumElements(0, s16, HasBWI ? 32 : (HasAVX2 ? 16 : 8))
- .clampMaxNumElements(0, s32, HasAVX512 ? 16 : (HasAVX2 ? 8 : 4))
- .clampMaxNumElements(0, s64, HasAVX512 ? 8 : (HasAVX2 ? 4 : 2))
+ .clampMaxNumElements(0, s8, HasAVX512 ? 64 : (HasAVX ? 32 : 16))
+ .clampMaxNumElements(0, s16, HasAVX512 ? 32 : (HasAVX ? 16 : 8))
+ .clampMaxNumElements(0, s32, HasAVX512 ? 16 : (HasAVX ? 8 : 4))
+ .clampMaxNumElements(0, s64, HasAVX512 ? 8 : (HasAVX ? 4 : 2))
.clampMaxNumElements(0, p0,
Is64Bit ? s64MaxVector.getNumElements()
: s32MaxVector.getNumElements())
>From 381281a5fe4bd8a929769e023a789230481843fa Mon Sep 17 00:00:00 2001
From: bonsthie <barnabe.bonnet at gmail.com>
Date: Fri, 3 Oct 2025 13:16:20 +0200
Subject: [PATCH 3/4] [X86][GISel] Merge builders for G_IMPLICIT_DEF, G_PHI,
G_FREEZE, and G_CONSTANT_FOLD_BARRIER
Unify the legality rule sets for value-transport operations (G_IMPLICIT_DEF, G_PHI, G_FREEZE, and G_CONSTANT_FOLD_BARRIER).
These instructions only define/carry values and should therefore accept the same set of legal types.
---
.../lib/Target/X86/GISel/X86LegalizerInfo.cpp | 31 +++----------------
.../CodeGen/X86/GlobalISel/legalize-phi.mir | 14 ++++-----
2 files changed, 11 insertions(+), 34 deletions(-)
diff --git a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
index b7da9609e962e..ab5d3e6c04929 100644
--- a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
+++ b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
@@ -89,8 +89,10 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
// 32/64-bits needs support for s64/s128 to handle cases:
// s64 = EXTEND (G_IMPLICIT_DEF s32) -> s64 = G_IMPLICIT_DEF
// s128 = EXTEND (G_IMPLICIT_DEF s32/s64) -> s128 = G_IMPLICIT_DEF
- getActionDefinitionsBuilder(G_IMPLICIT_DEF)
+ getActionDefinitionsBuilder(
+ {G_IMPLICIT_DEF, G_PHI, G_FREEZE, G_CONSTANT_FOLD_BARRIER})
.legalFor({p0, s1, s8, s16, s32, s64})
+ .legalFor(UseX87, {s80})
.legalFor(Is64Bit, {s128})
.legalFor(HasSSE2, {v16s8, v8s16, v4s32, v2s64})
.legalFor(HasAVX, {v32s8, v16s16, v8s32, v4s64})
@@ -103,7 +105,7 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
.clampMinNumElements(0, s32, 4)
.clampMinNumElements(0, s64, 2)
.clampMaxNumElements(0, s8, HasAVX512 ? 64 : (HasAVX ? 32 : 16))
- .clampMaxNumElements(0, s16, HasAVX512 ? 32 : (HasAVX ? 16 : 8))
+ .clampMaxNumElements(0, s16, HasAVX512 ? 32 : (HasAVX ? 16 : 8))
.clampMaxNumElements(0, s32, HasAVX512 ? 16 : (HasAVX ? 8 : 4))
.clampMaxNumElements(0, s64, HasAVX512 ? 8 : (HasAVX ? 4 : 2))
.clampMaxNumElements(0, p0,
@@ -303,26 +305,6 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
.clampScalar(1, s16, sMaxScalar)
.scalarSameSizeAs(0, 1);
- // control flow
- getActionDefinitionsBuilder(G_PHI)
- .legalFor({s8, s16, s32, p0})
- .legalFor(UseX87, {s80})
- .legalFor(Is64Bit, {s64})
- .legalFor(HasSSE1, {v16s8, v8s16, v4s32, v2s64})
- .legalFor(HasAVX, {v32s8, v16s16, v8s32, v4s64})
- .legalFor(HasAVX512, {v64s8, v32s16, v16s32, v8s64})
- .clampMinNumElements(0, s8, 16)
- .clampMinNumElements(0, s16, 8)
- .clampMinNumElements(0, s32, 4)
- .clampMinNumElements(0, s64, 2)
- .clampMaxNumElements(0, s8, HasAVX512 ? 64 : (HasAVX ? 32 : 16))
- .clampMaxNumElements(0, s16, HasAVX512 ? 32 : (HasAVX ? 16 : 8))
- .clampMaxNumElements(0, s32, HasAVX512 ? 16 : (HasAVX ? 8 : 4))
- .clampMaxNumElements(0, s64, HasAVX512 ? 8 : (HasAVX ? 4 : 2))
- .widenScalarToNextPow2(0, /*Min=*/32)
- .clampScalar(0, s8, sMaxScalar)
- .scalarize(0);
-
getActionDefinitionsBuilder(G_BRCOND).legalFor({s1});
// pointer handling
@@ -606,11 +588,6 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
.minScalar(0, LLT::scalar(32))
.libcall();
- getActionDefinitionsBuilder({G_FREEZE, G_CONSTANT_FOLD_BARRIER})
- .legalFor({s8, s16, s32, s64, p0})
- .widenScalarToNextPow2(0, /*Min=*/8)
- .clampScalar(0, s8, sMaxScalar);
-
getLegacyLegalizerInfo().computeTables();
verify(*STI.getInstrInfo());
}
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir
index 31de686878a97..92e458896c8d8 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir
@@ -148,21 +148,21 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $edx
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s8)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: G_BRCOND [[TRUNC]](s1), %bb.2
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s8)
+ ; CHECK-NEXT: G_BRCOND [[TRUNC1]](s1), %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.cond.false:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
- ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.cond.end:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s8) = G_PHI [[TRUNC2]](s8), %bb.1, [[TRUNC1]](s8), %bb.0
- ; CHECK-NEXT: $al = COPY [[PHI]](s8)
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s1) = G_PHI [[TRUNC2]](s1), %bb.1, [[TRUNC]](s1), %bb.0
+ ; CHECK-NEXT: [[EXT:%[0-9]+]]:_(s8) = G_ANYEXT [[PHI]](s1)
+ ; CHECK-NEXT: $al = COPY [[EXT]](s8)
; CHECK-NEXT: RET 0, implicit $al
bb.1.entry:
successors: %bb.3(0x40000000), %bb.2(0x40000000)
>From 614e8758ef06a48ece9603f4d7faf1789c84612f Mon Sep 17 00:00:00 2001
From: bonsthie <barnabe.bonnet at gmail.com>
Date: Sat, 4 Oct 2025 18:35:27 +0200
Subject: [PATCH 4/4] [X86][GISel] Support G_FREEZE and G_CONSTANT_FOLD_BARRIER
selection
- Teach the X86 GlobalISel selector to lower G_FREEZE as a plain COPY, since it
has no side effects after legalization.
- Add tests to verify selection of G_FREEZE -> COPY and missing coverage for
G_CONSTANT_FOLD_BARRIER -> COPY.
- Rename legalize-g_implicit_def.mir to legalize-undef-vec-scaling.mir to align
with existing naming conventions.
---
.../X86/GISel/X86InstructionSelector.cpp | 1 +
...def.mir => legalize-undef-vec-scaling.mir} | 0
.../select-constant-fold-barrier-vec256.mir | 23 ++++++
.../select-constant-fold-barrier-vec512.mir | 23 ++++++
.../select-constant-fold-barrier.mir | 77 +++++++++++++++++++
.../X86/GlobalISel/select-freeze-vec256.mir | 23 ++++++
.../X86/GlobalISel/select-freeze-vec512.mir | 23 ++++++
.../CodeGen/X86/GlobalISel/select-freeze.mir | 77 +++++++++++++++++++
8 files changed, 247 insertions(+)
rename llvm/test/CodeGen/X86/GlobalISel/{legalize-g_implicit_def.mir => legalize-undef-vec-scaling.mir} (100%)
create mode 100644 llvm/test/CodeGen/X86/GlobalISel/select-constant-fold-barrier-vec256.mir
create mode 100644 llvm/test/CodeGen/X86/GlobalISel/select-constant-fold-barrier-vec512.mir
create mode 100644 llvm/test/CodeGen/X86/GlobalISel/select-constant-fold-barrier.mir
create mode 100644 llvm/test/CodeGen/X86/GlobalISel/select-freeze-vec256.mir
create mode 100644 llvm/test/CodeGen/X86/GlobalISel/select-freeze-vec512.mir
create mode 100644 llvm/test/CodeGen/X86/GlobalISel/select-freeze.mir
diff --git a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
index 3090ad313b90d..27fba34b58e5d 100644
--- a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
+++ b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
@@ -407,6 +407,7 @@ bool X86InstructionSelector::select(MachineInstr &I) {
case TargetOpcode::G_TRUNC:
return selectTruncOrPtrToInt(I, MRI, MF);
case TargetOpcode::G_INTTOPTR:
+ case TargetOpcode::G_FREEZE:
return selectCopy(I, MRI);
case TargetOpcode::G_ZEXT:
return selectZext(I, MRI, MF);
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-g_implicit_def.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-undef-vec-scaling.mir
similarity index 100%
rename from llvm/test/CodeGen/X86/GlobalISel/legalize-g_implicit_def.mir
rename to llvm/test/CodeGen/X86/GlobalISel/legalize-undef-vec-scaling.mir
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-constant-fold-barrier-vec256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-constant-fold-barrier-vec256.mir
new file mode 100644
index 0000000000000..254c1b65f9e63
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-constant-fold-barrier-vec256.mir
@@ -0,0 +1,23 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: select_cfb_vec256
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
+ - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
+body: |
+ bb.0:
+ liveins: $ymm0
+
+ ; CHECK-LABEL: name: select_cfb_vec256
+ ; CHECK: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+ ; CHECK-NOT: G_CONSTANT_FOLD_BARRIER
+ ; CHECK-NEXT: $ymm1 = COPY [[COPY]]
+ ; CHECK-NEXT: RET 0, implicit $ymm1
+ %0:vecr(<8 x s32>) = COPY $ymm0
+ %1:vecr(<8 x s32>) = G_CONSTANT_FOLD_BARRIER %0
+ $ymm1 = COPY %1(<8 x s32>)
+ RET 0, implicit $ymm1
+...
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-constant-fold-barrier-vec512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-constant-fold-barrier-vec512.mir
new file mode 100644
index 0000000000000..3da354ba3934e
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-constant-fold-barrier-vec512.mir
@@ -0,0 +1,23 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: select_cfb_vec512
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
+ - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
+body: |
+ bb.0:
+ liveins: $zmm0
+
+ ; CHECK-LABEL: name: select_cfb_vec512
+ ; CHECK: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+ ; CHECK-NOT: G_CONSTANT_FOLD_BARRIER
+ ; CHECK-NEXT: $zmm1 = COPY [[COPY]]
+ ; CHECK-NEXT: RET 0, implicit $zmm1
+ %0:vecr(<8 x s64>) = COPY $zmm0
+ %1:vecr(<8 x s64>) = G_CONSTANT_FOLD_BARRIER %0
+ $zmm1 = COPY %1(<8 x s64>)
+ RET 0, implicit $zmm1
+...
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-constant-fold-barrier.mir b/llvm/test/CodeGen/X86/GlobalISel/select-constant-fold-barrier.mir
new file mode 100644
index 0000000000000..fa012f9209d6e
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-constant-fold-barrier.mir
@@ -0,0 +1,77 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+
+---
+name: select_cfb_scalar_s32
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '', flags: [ ] }
+ - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
+liveins:
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0:
+ liveins: $edi
+
+ ; CHECK-LABEL: name: select_cfb_scalar_s32
+ ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK-NOT: G_CONSTANT_FOLD_BARRIER
+ ; CHECK-NEXT: $eax = COPY [[COPY]]
+ ; CHECK-NEXT: RET 0, implicit $eax
+ %0:gpr(s32) = COPY $edi
+ %1:gpr(s32) = G_CONSTANT_FOLD_BARRIER %0
+ $eax = COPY %1(s32)
+ RET 0, implicit $eax
+...
+
+---
+name: select_cfb_scalar_s64
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '', flags: [ ] }
+ - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
+liveins:
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0:
+ liveins: $rdi
+
+ ; CHECK-LABEL: name: select_cfb_scalar_s64
+ ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK-NOT: G_CONSTANT_FOLD_BARRIER
+ ; CHECK-NEXT: $rax = COPY [[COPY]]
+ ; CHECK-NEXT: RET 0, implicit $rax
+ %0:gpr(s64) = COPY $rdi
+ %1:gpr(s64) = G_CONSTANT_FOLD_BARRIER %0
+ $rax = COPY %1(s64)
+ RET 0, implicit $rax
+...
+
+
+---
+name: select_cfb_vec128
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
+ - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
+body: |
+ bb.0:
+ liveins: $xmm0
+
+ ; CHECK-LABEL: name: select_cfb_vec128
+ ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NOT: G_CONSTANT_FOLD_BARRIER
+ ; CHECK-NEXT: $xmm1 = COPY [[COPY]]
+ ; CHECK-NEXT: RET 0, implicit $xmm1
+ %0:vecr(<4 x s32>) = COPY $xmm0
+ %1:vecr(<4 x s32>) = G_CONSTANT_FOLD_BARRIER %0
+ $xmm1 = COPY %1(<4 x s32>)
+ RET 0, implicit $xmm1
+...
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-freeze-vec256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-freeze-vec256.mir
new file mode 100644
index 0000000000000..11251e4085cce
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-freeze-vec256.mir
@@ -0,0 +1,23 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: select_freeze_vec256
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
+ - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
+body: |
+ bb.0:
+ liveins: $ymm0
+
+ ; CHECK-LABEL: name: select_freeze_vec256
+ ; CHECK: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
+ ; CHECK-NOT: G_FREEZE
+ ; CHECK-NEXT: $ymm1 = COPY [[COPY]]
+ ; CHECK-NEXT: RET 0, implicit $ymm1
+ %0:vecr(<8 x s32>) = COPY $ymm0
+ %1:vecr(<8 x s32>) = G_FREEZE %0
+ $ymm1 = COPY %1(<8 x s32>)
+ RET 0, implicit $ymm1
+...
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-freeze-vec512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-freeze-vec512.mir
new file mode 100644
index 0000000000000..bcf299acef18b
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-freeze-vec512.mir
@@ -0,0 +1,23 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: select_freeze_vec512
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
+ - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
+body: |
+ bb.0:
+ liveins: $zmm0
+
+ ; CHECK-LABEL: name: select_freeze_vec512
+ ; CHECK: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
+ ; CHECK-NOT: G_FREEZE
+ ; CHECK-NEXT: $zmm1 = COPY [[COPY]]
+ ; CHECK-NEXT: RET 0, implicit $zmm1
+ %0:vecr(<8 x s64>) = COPY $zmm0
+ %1:vecr(<8 x s64>) = G_FREEZE %0
+ $zmm1 = COPY %1(<8 x s64>)
+ RET 0, implicit $zmm1
+...
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-freeze.mir b/llvm/test/CodeGen/X86/GlobalISel/select-freeze.mir
new file mode 100644
index 0000000000000..cf5ad47ccf338
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-freeze.mir
@@ -0,0 +1,77 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+
+---
+name: select_freeze_scalar_s32
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '', flags: [ ] }
+ - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
+liveins:
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0:
+ liveins: $edi
+
+ ; CHECK-LABEL: name: select_freeze_scalar_s32
+ ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK-NOT: G_FREEZE
+ ; CHECK-NEXT: $eax = COPY [[COPY]]
+ ; CHECK-NEXT: RET 0, implicit $eax
+ %0:gpr(s32) = COPY $edi
+ %1:gpr(s32) = G_FREEZE %0
+ $eax = COPY %1(s32)
+ RET 0, implicit $eax
+...
+
+---
+name: select_freeze_scalar_s64
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '', flags: [ ] }
+ - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
+liveins:
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0:
+ liveins: $rdi
+
+ ; CHECK-LABEL: name: select_freeze_scalar_s64
+ ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK-NOT: G_FREEZE
+ ; CHECK-NEXT: $rax = COPY [[COPY]]
+ ; CHECK-NEXT: RET 0, implicit $rax
+ %0:gpr(s64) = COPY $rdi
+ %1:gpr(s64) = G_FREEZE %0
+ $rax = COPY %1(s64)
+ RET 0, implicit $rax
+...
+
+
+---
+name: select_freeze_vec128
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
+ - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
+body: |
+ bb.0:
+ liveins: $xmm0
+
+ ; CHECK-LABEL: name: select_freeze_vec128
+ ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NOT: G_FREEZE
+ ; CHECK-NEXT: $xmm1 = COPY [[COPY]]
+ ; CHECK-NEXT: RET 0, implicit $xmm1
+ %0:vecr(<4 x s32>) = COPY $xmm0
+ %1:vecr(<4 x s32>) = G_FREEZE %0
+ $xmm1 = COPY %1(<4 x s32>)
+ RET 0, implicit $xmm1
+...
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