[llvm] [AMDGPU][True16][CodeGen] si-fix-sgpr-copies legalize size mismatched V2S copy with subreg case (PR #161290)

Brox Chen via llvm-commits llvm-commits at lists.llvm.org
Sat Oct 4 13:25:34 PDT 2025


================
@@ -131,6 +131,34 @@ body:             |
     %2:sreg_32 = S_TRUNC_F16 %1:sreg_32, implicit $mode
 ...
 
+---
+name:            copy_vgpr16_sreg32_lo16_usedby_salu16
+body:             |
+  bb.0:
+    ; GCN-LABEL: name: copy_vgpr16_sreg32_lo16_usedby_salu16
+    ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+    ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+    ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[DEF]].lo16, %subreg.lo16, [[DEF1]], %subreg.hi16
+    ; GCN-NEXT: [[V_TRUNC_F16_t16_e64_:%[0-9]+]]:vgpr_16 = V_TRUNC_F16_t16_e64 0, [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
+    %0:vgpr_32 = IMPLICIT_DEF
+    %1:sreg_32 = COPY %0.lo16:vgpr_32
----------------
broxigarchen wrote:

We are still emitting some illegal mir from isel. This happens when isel sometimes put 16bit into vgpr16 and sometimes in sreg32. We use uniform/divergent to try selecting different `trunc/ext/build_vector` patterns for sreg32 vs vgpr16, but they do not always match, i.e. the return from a load is vgpr but it's uniformed.

The current plan is to eliminate these illegal case in fix-sgpr-copies pass

https://github.com/llvm/llvm-project/pull/161290


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