[llvm] e95a571 - [RISCV] Add i32 to some QC_SHLADD patterns to reduce RISCVGenDAGISel.inc size. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2025-10-03T22:10:03-07:00
New Revision: e95a571f402074ac438235b13a4099f43c4e822c

URL: https://github.com/llvm/llvm-project/commit/e95a571f402074ac438235b13a4099f43c4e822c
DIFF: https://github.com/llvm/llvm-project/commit/e95a571f402074ac438235b13a4099f43c4e822c.diff

LOG: [RISCV] Add i32 to some QC_SHLADD patterns to reduce RISCVGenDAGISel.inc size. NFC

The shift amount type is independent of the output type. We need to
force it to i32 to prevent tablegen from creating an unnecessary
i64 pattern.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index efdbd1298aec6..447f05cf88788 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1417,9 +1417,9 @@ class SelectQCbi<CondCode Cond, DAGOperand InTyImm, Pseudo OpNode >
 let Predicates = [HasVendorXqciac, IsRV32] in {
 def : Pat<(i32 (add GPRNoX0:$rd, (mul GPRNoX0:$rs1, simm12_lo:$imm12))),
           (QC_MULIADD GPRNoX0:$rd, GPRNoX0:$rs1, simm12_lo:$imm12)>;
-def : Pat<(i32 (add_like_non_imm12 (shl GPRNoX0:$rs1, uimm5gt3:$imm), GPRNoX0:$rs2)),
+def : Pat<(i32 (add_like_non_imm12 (shl GPRNoX0:$rs1, (i32 uimm5gt3:$imm)), GPRNoX0:$rs2)),
           (QC_SHLADD GPRNoX0:$rs1, GPRNoX0:$rs2, uimm5gt3:$imm)>;
-def : Pat<(i32 (riscv_shl_add GPRNoX0:$rs1, uimm5gt3:$imm, GPRNoX0:$rs2)),
+def : Pat<(i32 (riscv_shl_add GPRNoX0:$rs1, (i32 uimm5gt3:$imm), GPRNoX0:$rs2)),
           (QC_SHLADD GPRNoX0:$rs1, GPRNoX0:$rs2, uimm5gt3:$imm)>;
 } // Predicates = [HasVendorXqciac, IsRV32]