[llvm] 9c118aa - [RISCV] Remove unusable pattern from RISCVGISel.td. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2025-10-03T14:37:46-07:00
New Revision: 9c118aa6a6fedb1006a3a81ebca40f226e5abf93

URL: https://github.com/llvm/llvm-project/commit/9c118aa6a6fedb1006a3a81ebca40f226e5abf93
DIFF: https://github.com/llvm/llvm-project/commit/9c118aa6a6fedb1006a3a81ebca40f226e5abf93.diff

LOG: [RISCV] Remove unusable pattern from RISCVGISel.td. NFC

This pattern doesn't have a GISelPredicateCode so it's only usable
in SDAG.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVGISel.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index 9e833b762bd42..7f5d0af565355 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -126,11 +126,6 @@ let Predicates = [HasAtomicLdSt, IsRV64] in {
 // RV64 i32 patterns not used by SelectionDAG
 //===----------------------------------------------------------------------===//
 
-def zext_is_sext : PatFrag<(ops node:$src), (zext node:$src), [{
-  KnownBits Known = CurDAG->computeKnownBits(N->getOperand(0), 0);
-  return Known.isNonNegative();
-}]>;
-
 let Predicates = [IsRV64] in {
 def : LdPat<extloadi8, LBU, i32>; // Prefer unsigned due to no c.lb in Zcb.
 def : LdPat<extloadi16, LH, i32>;
@@ -142,9 +137,6 @@ def : Pat<(sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;
 
 def : Pat<(sext_inreg (i64 (add GPR:$rs1, simm12_lo:$imm)), i32),
           (ADDIW GPR:$rs1, simm12_lo:$imm)>;
-
-// Use sext if the sign bit of the input is 0.
-def : Pat<(zext_is_sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;
 }
 
 let Predicates = [IsRV64, NoStdExtZba] in