[llvm] 2e67f5c - [SLP][NFC]Add udiv/srem test cases, NFC

[Alexey Bataev via llvm-commits]

Author: Alexey Bataev
Date: 2025-10-03T10:49:16-07:00
New Revision: 2e67f5ceb8585983e1ca64e776bcbdb86b27c61f

URL: https://github.com/llvm/llvm-project/commit/2e67f5ceb8585983e1ca64e776bcbdb86b27c61f
DIFF: https://github.com/llvm/llvm-project/commit/2e67f5ceb8585983e1ca64e776bcbdb86b27c61f.diff

LOG: [SLP][NFC]Add udiv/srem test cases, NFC

Added: 
    

Modified: 
    llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll b/llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll
index ed0bd3f38ead7..cf62fd5cf66f7 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll
@@ -55,6 +55,54 @@ entry:
   ret void
 }
 
+define void @test_add_udiv(ptr %arr1, ptr %arr2, i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
+; CHECK-LABEL: @test_add_udiv(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[GEP1_2:%.*]] = getelementptr i32, ptr [[ARR1:%.*]], i32 2
+; CHECK-NEXT:    [[GEP1_3:%.*]] = getelementptr i32, ptr [[ARR1]], i32 3
+; CHECK-NEXT:    [[V2:%.*]] = load i32, ptr [[GEP1_2]], align 4
+; CHECK-NEXT:    [[V3:%.*]] = load i32, ptr [[GEP1_3]], align 4
+; CHECK-NEXT:    [[Y2:%.*]] = add nsw i32 [[A2:%.*]], 42
+; CHECK-NEXT:    [[TMP0:%.*]] = load <2 x i32>, ptr [[ARR1]], align 4
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[A0:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A1:%.*]], i32 1
+; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[A3:%.*]], i32 3
+; CHECK-NEXT:    [[TMP4:%.*]] = add nsw <4 x i32> <i32 1146, i32 146, i32 0, i32 0>, [[TMP3]]
+; CHECK-NEXT:    [[RES2:%.*]] = udiv i32 [[V2]], [[Y2]]
+; CHECK-NEXT:    [[TMP5:%.*]] = insertelement <4 x i32> poison, i32 [[RES2]], i32 2
+; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[V3]], i32 3
+; CHECK-NEXT:    [[TMP7:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
+; CHECK-NEXT:    [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> [[TMP7]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+; CHECK-NEXT:    [[TMP9:%.*]] = add nsw <4 x i32> [[TMP8]], [[TMP4]]
+; CHECK-NEXT:    store <4 x i32> [[TMP9]], ptr [[ARR2:%.*]], align 4
+; CHECK-NEXT:    ret void
+;
+entry:
+  %gep1.1 = getelementptr i32, ptr %arr1, i32 1
+  %gep1.2 = getelementptr i32, ptr %arr1, i32 2
+  %gep1.3 = getelementptr i32, ptr %arr1, i32 3
+  %gep2.1 = getelementptr i32, ptr %arr2, i32 1
+  %gep2.2 = getelementptr i32, ptr %arr2, i32 2
+  %gep2.3 = getelementptr i32, ptr %arr2, i32 3
+  %v0 = load i32, ptr %arr1
+  %v1 = load i32, ptr %gep1.1
+  %v2 = load i32, ptr %gep1.2
+  %v3 = load i32, ptr %gep1.3
+  %y0 = add nsw i32 %a0, 1146
+  %y1 = add nsw i32 %a1, 146
+  %y2 = add nsw i32 %a2, 42
+  %y3 = add nsw i32 %a3, 0
+  %res0 = add nsw i32 %v0, %y0
+  %res1 = add nsw i32 %v1, %y1
+  %res2 = udiv i32 %v2, %y2
+  %res3 = add nsw i32 %v3, %y3
+  store i32 %res0, ptr %arr2
+  store i32 %res1, ptr %gep2.1
+  store i32 %res2, ptr %gep2.2
+  store i32 %res3, ptr %gep2.3
+  ret void
+}
+
 ;; Similar test, but now div/rem is main opcode and not the alternate one. Same issue.
 define void @test_urem_add(ptr %arr1, ptr %arr2, i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
 ; CHECK-LABEL: @test_urem_add(
@@ -114,3 +162,56 @@ entry:
   store i32 %res3, ptr %gep2.3
   ret void
 }
+
+define void @test_srem_add(ptr %arr1, ptr %arr2, i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
+; CHECK-LABEL: @test_srem_add(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[GEP1_1:%.*]] = getelementptr i32, ptr [[ARR1:%.*]], i32 1
+; CHECK-NEXT:    [[GEP1_2:%.*]] = getelementptr i32, ptr [[ARR1]], i32 2
+; CHECK-NEXT:    [[GEP1_3:%.*]] = getelementptr i32, ptr [[ARR1]], i32 3
+; CHECK-NEXT:    [[GEP2_1:%.*]] = getelementptr i32, ptr [[ARR2:%.*]], i32 1
+; CHECK-NEXT:    [[GEP2_2:%.*]] = getelementptr i32, ptr [[ARR2]], i32 2
+; CHECK-NEXT:    [[GEP2_3:%.*]] = getelementptr i32, ptr [[ARR2]], i32 3
+; CHECK-NEXT:    [[V0:%.*]] = load i32, ptr [[ARR1]], align 4
+; CHECK-NEXT:    [[V1:%.*]] = load i32, ptr [[GEP1_1]], align 4
+; CHECK-NEXT:    [[V2:%.*]] = load i32, ptr [[GEP1_2]], align 4
+; CHECK-NEXT:    [[V3:%.*]] = load i32, ptr [[GEP1_3]], align 4
+; CHECK-NEXT:    [[Y0:%.*]] = add nsw i32 [[A0:%.*]], 1146
+; CHECK-NEXT:    [[Y1:%.*]] = add nsw i32 [[A1:%.*]], 146
+; CHECK-NEXT:    [[Y2:%.*]] = add nsw i32 [[A2:%.*]], 42
+; CHECK-NEXT:    [[Y3:%.*]] = add nsw i32 [[A3:%.*]], 0
+; CHECK-NEXT:    [[RES0:%.*]] = srem i32 [[V0]], [[Y0]]
+; CHECK-NEXT:    [[RES1:%.*]] = srem i32 [[V1]], [[Y1]]
+; CHECK-NEXT:    [[RES2:%.*]] = srem i32 [[V2]], [[Y2]]
+; CHECK-NEXT:    [[RES3:%.*]] = add nsw i32 [[V3]], [[Y3]]
+; CHECK-NEXT:    store i32 [[RES0]], ptr [[ARR2]], align 4
+; CHECK-NEXT:    store i32 [[RES1]], ptr [[GEP2_1]], align 4
+; CHECK-NEXT:    store i32 [[RES2]], ptr [[GEP2_2]], align 4
+; CHECK-NEXT:    store i32 [[RES3]], ptr [[GEP2_3]], align 4
+; CHECK-NEXT:    ret void
+;
+entry:
+  %gep1.1 = getelementptr i32, ptr %arr1, i32 1
+  %gep1.2 = getelementptr i32, ptr %arr1, i32 2
+  %gep1.3 = getelementptr i32, ptr %arr1, i32 3
+  %gep2.1 = getelementptr i32, ptr %arr2, i32 1
+  %gep2.2 = getelementptr i32, ptr %arr2, i32 2
+  %gep2.3 = getelementptr i32, ptr %arr2, i32 3
+  %v0 = load i32, ptr %arr1
+  %v1 = load i32, ptr %gep1.1
+  %v2 = load i32, ptr %gep1.2
+  %v3 = load i32, ptr %gep1.3
+  %y0 = add nsw i32 %a0, 1146
+  %y1 = add nsw i32 %a1, 146
+  %y2 = add nsw i32 %a2, 42
+  %y3 = add nsw i32 %a3, 0
+  %res0 = srem i32 %v0, %y0
+  %res1 = srem i32 %v1, %y1
+  %res2 = srem i32 %v2, %y2
+  %res3 = add nsw i32 %v3, %y3
+  store i32 %res0, ptr %arr2
+  store i32 %res1, ptr %gep2.1
+  store i32 %res2, ptr %gep2.2
+  store i32 %res3, ptr %gep2.3
+  ret void
+}