[llvm] [RISCV] Replace uses of RISCV::NoRegister with Register(), isValid(), or operator bool. NFC (PR #161781)

[Craig Topper via llvm-commits]

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@@ -1560,7 +1560,7 @@ static MCRegister getRVVBaseRegister(const RISCVRegisterInfo &TRI,
   MCRegister BaseReg = TRI.getSubReg(Reg, RISCV::sub_vrm1_0);
   // If it's not a grouped vector register, it doesn't have subregister, so
   // the base register is just itself.
-  if (BaseReg == RISCV::NoRegister)
+  if (!BaseReg)
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topperc wrote:

In my prior conversations with @arsenm, I think we decided that we will add an `operator bool` when we remove `operator unsigned`.

https://github.com/llvm/llvm-project/pull/161781