[llvm] [TableGen] Look up registers directly in the CodeGenRegBank in CompressInstEmitter, rather than indirecting via the name. (PR #161853)

[Owen Anderson via llvm-commits]

https://github.com/resistor created https://github.com/llvm/llvm-project/pull/161853

The previous code was subtly incorrect, as it indexed the RegistersByName map using the tblgen Def name of the register, rather than the AsmName with which the table was initialized. But all of this indirection via the name was unnecessary.


>From ad5d38361894ad379c9f3a24d2e7d30f0ae7cedf Mon Sep 17 00:00:00 2001
From: Owen Anderson <resistor at mac.com>
Date: Fri, 3 Oct 2025 21:23:10 +0900
Subject: [PATCH] [TableGen] Look up registers directly in the CodeGenRegBank
 in CompressInstEmitter, rather than indirecting via the name.

The previous code was subtly incorrect, as it indexed the RegistersByName map using the tblgen Def name of the register, rather than the AsmName with which the table was initialized. But all of this indirection via the name was unnecessary.
---
 llvm/utils/TableGen/CompressInstEmitter.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp
index ccf83859924bc..d8c5ca7c1e1a3 100644
--- a/llvm/utils/TableGen/CompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/CompressInstEmitter.cpp
@@ -167,7 +167,7 @@ bool CompressInstEmitter::validateRegister(const Record *Reg,
   assert(RegClass->isSubClassOf("RegisterClass") &&
          "RegClass record should be a RegisterClass");
   const CodeGenRegisterClass &RC = Target.getRegisterClass(RegClass);
-  const CodeGenRegister *R = Target.getRegisterByName(Reg->getName().lower());
+  const CodeGenRegister *R = Target.getRegBank().getReg(Reg);
   assert(R != nullptr && "Register not defined!!");
   return RC.contains(R);
 }