[llvm] [AArch64] Add bitcasts for lowering saturating add/sub and shift intrinsics. (PR #161840)

[via llvm-commits]

Lukacma wrote:

This is my first attempt at implementing this part and I would appreciate your feedback on this approach as there are couple of things I am uncertain about here. 

Firstly, GlobalISel works fine with original intrinsics and doesn't require custom lowering of them, I decided to leave it be and instead duplicate patterns as you can see. (one which match new node for SDag and the other variant which matches original intrinsic). I am not sure if this is the correct approach or if I should lower to the new node also in GlobalISel. 

Secondly, I am not sure if creating new nodes is necessary here as well. I was thinking about abusing intrinsics a bit and adding floating point variants of them. For example sqadd intrinsic is defined like this:

```
DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
                [IntrNoMem]>;
```

I was thinking about generalizing it to allow it to be used with floating-point types, in which case I could lower into the floating-point variant and wouldn't need to create new ISD nodes. This should also resolve the issue with pattern duplication due to different lowerings, if I am not missing smth. I am not sure though whether such "abuse" is fine (I don't think it is, but it would make my life simpler).




https://github.com/llvm/llvm-project/pull/161840