[llvm] 5601c40 - AMDGPU: Stop trying to constrain register class of post-RA-pseudos (#161792)

[via llvm-commits]

Author: Matt Arsenault
Date: 2025-10-03T21:19:33+09:00
New Revision: 5601c4080abfdd362415cb0406de64c685edca67

URL: https://github.com/llvm/llvm-project/commit/5601c4080abfdd362415cb0406de64c685edca67
DIFF: https://github.com/llvm/llvm-project/commit/5601c4080abfdd362415cb0406de64c685edca67.diff

LOG: AMDGPU: Stop trying to constrain register class of post-RA-pseudos (#161792)

This is trying to constrain the register class of a physical register,
which makes no sense.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index fe6b8b96cbd57..cda8069936af2 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2112,8 +2112,6 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
 
   case AMDGPU::SI_RESTORE_S32_FROM_VGPR:
     MI.setDesc(get(AMDGPU::V_READLANE_B32));
-    MI.getMF()->getRegInfo().constrainRegClass(MI.getOperand(0).getReg(),
-                                               &AMDGPU::SReg_32_XM0RegClass);
     break;
   case AMDGPU::AV_MOV_B32_IMM_PSEUDO: {
     Register Dst = MI.getOperand(0).getReg();