[llvm] [AArch64] Improve codegen for partial.reduce.add v16i8 -> v2i32 (PR #161833)

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git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 056d367a1..a380646a1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -30774,8 +30774,8 @@ AArch64TargetLowering::LowerPARTIAL_REDUCE_MLA(SDValue Op,
   if (!ConvertToScalable && ResultVT == MVT::v2i32 && OpVT == MVT::v16i8) {
     SDValue ZeroVec = DAG.getConstant(0, DL, MVT::v4i32);
     SDValue WideAcc = DAG.getInsertSubvector(DL, ZeroVec, Acc, 0);
-    SDValue Wide = DAG.getNode(Op.getOpcode(), DL, MVT::v4i32,
-                               WideAcc, LHS, RHS);
+    SDValue Wide =
+        DAG.getNode(Op.getOpcode(), DL, MVT::v4i32, WideAcc, LHS, RHS);
     SDValue Lo = DAG.getExtractSubvector(DL, MVT::v2i32, Wide, 0);
     SDValue Hi = DAG.getExtractSubvector(DL, MVT::v2i32, Wide, 2);
     return DAG.getNode(ISD::ADD, DL, ResultVT, Lo, Hi);

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https://github.com/llvm/llvm-project/pull/161833