[llvm] [AMDGPU] Add wave reduce intrinsics for float types - 1 (PR #161814)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 3 02:53:43 PDT 2025
github-actions[bot] wrote:
<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
:warning: C/C++ code formatter, clang-format found issues in your code. :warning:
<details>
<summary>
You can test this locally with the following command:
</summary>
``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AMDGPU/SIISelLowering.cpp
``````````
:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:
</details>
<details>
<summary>
View the diff from clang-format here.
</summary>
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 8c677eef4..cb21b946d 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5813,7 +5813,7 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
.addReg(Accumulator->getOperand(0).getReg())
.addImm(0) // src1 modifier
.addReg(LaneValVreg)
- .addImm(0) // clamp
+ .addImm(0) // clamp
.addImm(0); // omod
NewAccumulator = BuildMI(*ComputeLoop, I, DL,
TII->get(AMDGPU::V_READFIRSTLANE_B32), DstReg)
``````````
</details>
https://github.com/llvm/llvm-project/pull/161814
More information about the llvm-commits
mailing list