[llvm] [AArch64][SME] Enable `aarch64-split-sve-objects` with hazard padding (PR #161714)

[Sander de Smalen via llvm-commits]

================
@@ -68,13 +68,12 @@ entry:
 }
 
 ; SVE calling conventions
-; Predicate register spills end up in FP region, currently. This can be
-; mitigated with the -aarch64-enable-zpr-predicate-spills option.
+; Padding is placed predicate and fpr/zpr register spills, so only emit remarks when hazard padding is off.
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sdesmalen-arm wrote:

nit:
```suggestion
; Padding is placed between predicate and fpr/zpr register spills, so only emit remarks when hazard padding is off.
```

https://github.com/llvm/llvm-project/pull/161714