[llvm] 8744287 - [RISCV][GISel] Use relaxed_load/store in GISel atomic patterns. NFC (#161712)

[via llvm-commits]

Author: Craig Topper
Date: 2025-10-02T21:14:43-07:00
New Revision: 874428708f3bcf2fc8402b2aa0ca720c1b6cd3a6

URL: https://github.com/llvm/llvm-project/commit/874428708f3bcf2fc8402b2aa0ca720c1b6cd3a6
DIFF: https://github.com/llvm/llvm-project/commit/874428708f3bcf2fc8402b2aa0ca720c1b6cd3a6.diff

LOG: [RISCV][GISel] Use relaxed_load/store in GISel atomic patterns. NFC (#161712)

We have additional patterns for GISel because we need to make s16 and
s32 legal for load/store. GISel does not distinquish integer and FP
scalar types in LLT. We only know whether the load should be integer or
FP after register bank selection.

These patterns should have been updated to use relaxed_load/store when
the patterns in RISCVInstrInfoA.td were updated. Without this we will
miscompile loads/stores with strong memory ordering when Zalasr is
enabled.

This patch just fixes the miscompile, Zalasr will now cause a GISel
abort in some cases. A follow up patch will add additional GISel
patterns for Zalasr.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVGISel.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index af1ceb6bcda4e..cf6f83a09610d 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -110,16 +110,16 @@ def : StPat<truncstorei8, SB, GPR, i16>;
 
 let Predicates = [HasAtomicLdSt] in {
   // Prefer unsigned due to no c.lb in Zcb.
-  def : LdPat<atomic_load_aext_8,    LBU, i16>;
-  def : LdPat<atomic_load_nonext_16, LH,  i16>;
+  def : LdPat<relaxed_load<atomic_load_aext_8>,    LBU, i16>;
+  def : LdPat<relaxed_load<atomic_load_nonext_16>, LH,  i16>;
 
-  def : StPat<atomic_store_8,  SB, GPR, i16>;
-  def : StPat<atomic_store_16, SH, GPR, i16>;
+  def : StPat<relaxed_store<atomic_store_8>,  SB, GPR, i16>;
+  def : StPat<relaxed_store<atomic_store_16>, SH, GPR, i16>;
 }
 
 let Predicates = [HasAtomicLdSt, IsRV64] in {
   // Load pattern is in RISCVInstrInfoA.td and shared with RV32.
-  def : StPat<atomic_store_32, SW, GPR, i32>;
+  def : StPat<relaxed_store<atomic_store_32>, SW, GPR, i32>;
 }
 
 //===----------------------------------------------------------------------===//