[llvm] [RISCV] Support scalar llvm.fmodf intrinsic. (PR #161743)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 2 21:08:29 PDT 2025
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/161743
>From c8591e43674fb3d8d70368c614c9e6992e03082f Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 2 Oct 2025 15:04:21 -0700
Subject: [PATCH 1/2] [RISCV] Support scalar llvm.fmodf intrinsic.
---
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +-
.../RISCV/GlobalISel/double-intrinsics.ll | 76 +++++++
.../RISCV/GlobalISel/float-intrinsics.ll | 79 +++++++
llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll | 31 +++
.../GlobalISel/legalizer-info-validation.mir | 5 +-
llvm/test/CodeGen/RISCV/double-intrinsics.ll | 108 ++++++++++
llvm/test/CodeGen/RISCV/float-intrinsics.ll | 109 ++++++++++
llvm/test/CodeGen/RISCV/fp128.ll | 49 +++++
llvm/test/CodeGen/RISCV/half-intrinsics.ll | 202 ++++++++++++++++++
10 files changed, 659 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 395d2c485af0e..662d3f6219033 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -629,7 +629,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
getActionDefinitionsBuilder({G_FCOS, G_FSIN, G_FTAN, G_FPOW, G_FLOG, G_FLOG2,
G_FLOG10, G_FEXP, G_FEXP2, G_FEXP10, G_FACOS,
G_FASIN, G_FATAN, G_FATAN2, G_FCOSH, G_FSINH,
- G_FTANH})
+ G_FTANH, G_FMODF})
.libcallFor({s32, s64})
.libcallFor(ST.is64Bit(), {s128});
getActionDefinitionsBuilder({G_FPOWI, G_FLDEXP})
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 50649cf3caba4..dcce2d29a7042 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -533,7 +533,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::FREM, ISD::FPOW, ISD::FPOWI,
ISD::FCOS, ISD::FSIN, ISD::FSINCOS, ISD::FEXP,
ISD::FEXP2, ISD::FEXP10, ISD::FLOG, ISD::FLOG2,
- ISD::FLOG10, ISD::FLDEXP, ISD::FFREXP},
+ ISD::FLOG10, ISD::FLDEXP, ISD::FFREXP, ISD::FMODF},
MVT::f16, Promote);
// FIXME: Need to promote f16 STRICT_* to f32 libcalls, but we don't have
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll b/llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
index 1469d49e210e0..f78bacb22973d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
@@ -1420,3 +1420,79 @@ define double @tanh_f64(double %a) nounwind {
%1 = call double @llvm.tanh.f64(double %a)
ret double %1
}
+
+define { double, double } @test_modf_f64(double %a) {
+; RV32IFD-LABEL: test_modf_f64:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: .cfi_def_cfa_offset 16
+; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IFD-NEXT: .cfi_offset ra, -4
+; RV32IFD-NEXT: mv a0, sp
+; RV32IFD-NEXT: call modf
+; RV32IFD-NEXT: fld fa1, 0(sp)
+; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IFD-NEXT: .cfi_restore ra
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: .cfi_def_cfa_offset 0
+; RV32IFD-NEXT: ret
+;
+; RV64IFD-LABEL: test_modf_f64:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: .cfi_def_cfa_offset 16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: .cfi_offset ra, -8
+; RV64IFD-NEXT: mv a0, sp
+; RV64IFD-NEXT: call modf
+; RV64IFD-NEXT: fld fa1, 0(sp)
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: .cfi_restore ra
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: .cfi_def_cfa_offset 0
+; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: test_modf_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: mv a1, a2
+; RV32I-NEXT: mv a2, sp
+; RV32I-NEXT: call modf
+; RV32I-NEXT: lw a2, 0(sp)
+; RV32I-NEXT: lw a3, 4(sp)
+; RV32I-NEXT: sw a0, 0(s0)
+; RV32I-NEXT: sw a1, 4(s0)
+; RV32I-NEXT: sw a2, 8(s0)
+; RV32I-NEXT: sw a3, 12(s0)
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .cfi_restore ra
+; RV32I-NEXT: .cfi_restore s0
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: .cfi_def_cfa_offset 0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_modf_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: mv a1, sp
+; RV64I-NEXT: call modf
+; RV64I-NEXT: ld a1, 0(sp)
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: .cfi_restore ra
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: .cfi_def_cfa_offset 0
+; RV64I-NEXT: ret
+ %result = call { double, double } @llvm.modf.f64(double %a)
+ ret { double, double } %result
+}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
index 23f660bb026a7..4b2758709fb84 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
@@ -2118,3 +2118,82 @@ define float @tanh_f32(float %a) nounwind {
%1 = call float @llvm.tanh.f32(float %a)
ret float %1
}
+
+define { float, float } @test_modf_f32(float %a) {
+; RV32IF-LABEL: test_modf_f32:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: .cfi_def_cfa_offset 16
+; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IF-NEXT: .cfi_offset ra, -4
+; RV32IF-NEXT: addi a0, sp, 8
+; RV32IF-NEXT: call modff
+; RV32IF-NEXT: flw fa1, 8(sp)
+; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IF-NEXT: .cfi_restore ra
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: .cfi_def_cfa_offset 0
+; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: test_modf_f32:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: .cfi_def_cfa_offset 16
+; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IF-NEXT: .cfi_offset ra, -8
+; RV64IF-NEXT: addi a0, sp, 4
+; RV64IF-NEXT: call modff
+; RV64IF-NEXT: flw fa1, 4(sp)
+; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IF-NEXT: .cfi_restore ra
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: .cfi_def_cfa_offset 0
+; RV64IF-NEXT: ret
+;
+; RV64IFD-LABEL: test_modf_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: .cfi_def_cfa_offset 16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: .cfi_offset ra, -8
+; RV64IFD-NEXT: addi a0, sp, 4
+; RV64IFD-NEXT: call modff
+; RV64IFD-NEXT: flw fa1, 4(sp)
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: .cfi_restore ra
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: .cfi_def_cfa_offset 0
+; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: test_modf_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: addi a1, sp, 8
+; RV32I-NEXT: call modff
+; RV32I-NEXT: lw a1, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .cfi_restore ra
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: .cfi_def_cfa_offset 0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_modf_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: call modff
+; RV64I-NEXT: lw a1, 4(sp)
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: .cfi_restore ra
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: .cfi_def_cfa_offset 0
+; RV64I-NEXT: ret
+ %result = call { float, float } @llvm.modf.f32(float %a)
+ ret { float, float } %result
+}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll b/llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
index ae9b6cc8948f5..f3716c9f80cdd 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
@@ -911,3 +911,34 @@ define fp128 @tanh(fp128 %a) nounwind {
%1 = call fp128 @llvm.tanh.f128(fp128 %a)
ret fp128 %1
}
+
+define { fp128, fp128 } @modf(fp128 %a) {
+; CHECK-LABEL: modf:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -32
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; CHECK-NEXT: .cfi_offset ra, -8
+; CHECK-NEXT: .cfi_offset s0, -16
+; CHECK-NEXT: mv s0, a0
+; CHECK-NEXT: mv a0, a1
+; CHECK-NEXT: mv a1, a2
+; CHECK-NEXT: mv a2, sp
+; CHECK-NEXT: call modfl
+; CHECK-NEXT: ld a2, 0(sp)
+; CHECK-NEXT: ld a3, 8(sp)
+; CHECK-NEXT: sd a0, 0(s0)
+; CHECK-NEXT: sd a1, 8(s0)
+; CHECK-NEXT: sd a2, 16(s0)
+; CHECK-NEXT: sd a3, 24(s0)
+; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT: .cfi_restore ra
+; CHECK-NEXT: .cfi_restore s0
+; CHECK-NEXT: addi sp, sp, 32
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %result = call { fp128, fp128 } @llvm.modf.f128(fp128 %a)
+ ret { fp128, fp128 } %result
+}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
index f1d17f9f02b90..1361d92239db5 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
@@ -506,8 +506,9 @@
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: G_FMODF (opcode {{[0-9]+}}): 1 type index, 0 imm indices
-# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
+# DEBUG-NEXT: .. the first uncovered type index: 1, OK
+# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: G_FPOW (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
diff --git a/llvm/test/CodeGen/RISCV/double-intrinsics.ll b/llvm/test/CodeGen/RISCV/double-intrinsics.ll
index caeb6e6ce70af..e1a9bf49b16e2 100644
--- a/llvm/test/CodeGen/RISCV/double-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/double-intrinsics.ll
@@ -2109,3 +2109,111 @@ define double @tanh_f64(double %a) nounwind {
%1 = call double @llvm.tanh.f64(double %a)
ret double %1
}
+
+define { double, double } @test_modf_f64(double %a) {
+; RV32IFD-LABEL: test_modf_f64:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: .cfi_def_cfa_offset 16
+; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IFD-NEXT: .cfi_offset ra, -4
+; RV32IFD-NEXT: mv a0, sp
+; RV32IFD-NEXT: call modf
+; RV32IFD-NEXT: fld fa1, 0(sp)
+; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IFD-NEXT: .cfi_restore ra
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: .cfi_def_cfa_offset 0
+; RV32IFD-NEXT: ret
+;
+; RV64IFD-LABEL: test_modf_f64:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: .cfi_def_cfa_offset 16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: .cfi_offset ra, -8
+; RV64IFD-NEXT: mv a0, sp
+; RV64IFD-NEXT: call modf
+; RV64IFD-NEXT: fld fa1, 0(sp)
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: .cfi_restore ra
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: .cfi_def_cfa_offset 0
+; RV64IFD-NEXT: ret
+;
+; RV32IZFINXZDINX-LABEL: test_modf_f64:
+; RV32IZFINXZDINX: # %bb.0:
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
+; RV32IZFINXZDINX-NEXT: mv a2, sp
+; RV32IZFINXZDINX-NEXT: call modf
+; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
+; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
+; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: .cfi_restore ra
+; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
+; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFINXZDINX-NEXT: ret
+;
+; RV64IZFINXZDINX-LABEL: test_modf_f64:
+; RV64IZFINXZDINX: # %bb.0:
+; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV64IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
+; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINXZDINX-NEXT: .cfi_offset ra, -8
+; RV64IZFINXZDINX-NEXT: mv a1, sp
+; RV64IZFINXZDINX-NEXT: call modf
+; RV64IZFINXZDINX-NEXT: ld a1, 0(sp)
+; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINXZDINX-NEXT: .cfi_restore ra
+; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
+; RV64IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0
+; RV64IZFINXZDINX-NEXT: ret
+;
+; RV32I-LABEL: test_modf_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: mv a3, a2
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: mv a2, sp
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: mv a1, a3
+; RV32I-NEXT: call modf
+; RV32I-NEXT: lw a2, 0(sp)
+; RV32I-NEXT: lw a3, 4(sp)
+; RV32I-NEXT: sw a0, 0(s0)
+; RV32I-NEXT: sw a1, 4(s0)
+; RV32I-NEXT: sw a2, 8(s0)
+; RV32I-NEXT: sw a3, 12(s0)
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .cfi_restore ra
+; RV32I-NEXT: .cfi_restore s0
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: .cfi_def_cfa_offset 0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_modf_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: mv a1, sp
+; RV64I-NEXT: call modf
+; RV64I-NEXT: ld a1, 0(sp)
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: .cfi_restore ra
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: .cfi_def_cfa_offset 0
+; RV64I-NEXT: ret
+ %result = call { double, double } @llvm.modf.f64(double %a)
+ ret { double, double } %result
+}
diff --git a/llvm/test/CodeGen/RISCV/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/float-intrinsics.ll
index b1230ae9dd6bf..bfeaa7d70aff2 100644
--- a/llvm/test/CodeGen/RISCV/float-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/float-intrinsics.ll
@@ -3050,3 +3050,112 @@ define float @tanh_f32(float %a) nounwind {
%1 = call float @llvm.tanh.f32(float %a)
ret float %1
}
+
+define { float, float } @test_modf_f32(float %a) {
+; RV32IF-LABEL: test_modf_f32:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: .cfi_def_cfa_offset 16
+; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IF-NEXT: .cfi_offset ra, -4
+; RV32IF-NEXT: addi a0, sp, 8
+; RV32IF-NEXT: call modff
+; RV32IF-NEXT: flw fa1, 8(sp)
+; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IF-NEXT: .cfi_restore ra
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: .cfi_def_cfa_offset 0
+; RV32IF-NEXT: ret
+;
+; RV32IZFINX-LABEL: test_modf_f32:
+; RV32IZFINX: # %bb.0:
+; RV32IZFINX-NEXT: addi sp, sp, -16
+; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16
+; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINX-NEXT: .cfi_offset ra, -4
+; RV32IZFINX-NEXT: addi a1, sp, 8
+; RV32IZFINX-NEXT: call modff
+; RV32IZFINX-NEXT: lw a1, 8(sp)
+; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINX-NEXT: .cfi_restore ra
+; RV32IZFINX-NEXT: addi sp, sp, 16
+; RV32IZFINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFINX-NEXT: ret
+;
+; RV64IF-LABEL: test_modf_f32:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: .cfi_def_cfa_offset 16
+; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IF-NEXT: .cfi_offset ra, -8
+; RV64IF-NEXT: addi a0, sp, 4
+; RV64IF-NEXT: call modff
+; RV64IF-NEXT: flw fa1, 4(sp)
+; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IF-NEXT: .cfi_restore ra
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: .cfi_def_cfa_offset 0
+; RV64IF-NEXT: ret
+;
+; RV64IZFINX-LABEL: test_modf_f32:
+; RV64IZFINX: # %bb.0:
+; RV64IZFINX-NEXT: addi sp, sp, -16
+; RV64IZFINX-NEXT: .cfi_def_cfa_offset 16
+; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINX-NEXT: .cfi_offset ra, -8
+; RV64IZFINX-NEXT: addi a1, sp, 4
+; RV64IZFINX-NEXT: call modff
+; RV64IZFINX-NEXT: lw a1, 4(sp)
+; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINX-NEXT: .cfi_restore ra
+; RV64IZFINX-NEXT: addi sp, sp, 16
+; RV64IZFINX-NEXT: .cfi_def_cfa_offset 0
+; RV64IZFINX-NEXT: ret
+;
+; RV64IFD-LABEL: test_modf_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: .cfi_def_cfa_offset 16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: .cfi_offset ra, -8
+; RV64IFD-NEXT: addi a0, sp, 4
+; RV64IFD-NEXT: call modff
+; RV64IFD-NEXT: flw fa1, 4(sp)
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: .cfi_restore ra
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: .cfi_def_cfa_offset 0
+; RV64IFD-NEXT: ret
+;
+; RV32I-LABEL: test_modf_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: addi a1, sp, 8
+; RV32I-NEXT: call modff
+; RV32I-NEXT: lw a1, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .cfi_restore ra
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: .cfi_def_cfa_offset 0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_modf_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: call modff
+; RV64I-NEXT: lw a1, 4(sp)
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: .cfi_restore ra
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: .cfi_def_cfa_offset 0
+; RV64I-NEXT: ret
+ %result = call { float, float } @llvm.modf.f32(float %a)
+ ret { float, float } %result
+}
diff --git a/llvm/test/CodeGen/RISCV/fp128.ll b/llvm/test/CodeGen/RISCV/fp128.ll
index a8e26f7686e50..db03a9b0bf42d 100644
--- a/llvm/test/CodeGen/RISCV/fp128.ll
+++ b/llvm/test/CodeGen/RISCV/fp128.ll
@@ -189,3 +189,52 @@ define fp128 @fminimum(fp128 %x, fp128 %y) {
%a = call fp128 @llvm.minimum.fp128(fp128 %x, fp128 %y)
ret fp128 %a
}
+
+define { fp128, fp128 } @modf(fp128 %a) {
+; RV32I-LABEL: modf:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -64
+; RV32I-NEXT: .cfi_def_cfa_offset 64
+; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: lw a3, 0(a1)
+; RV32I-NEXT: lw a4, 4(a1)
+; RV32I-NEXT: lw a5, 8(a1)
+; RV32I-NEXT: lw a6, 12(a1)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: addi a0, sp, 24
+; RV32I-NEXT: addi a1, sp, 8
+; RV32I-NEXT: addi a2, sp, 40
+; RV32I-NEXT: sw a3, 8(sp)
+; RV32I-NEXT: sw a4, 12(sp)
+; RV32I-NEXT: sw a5, 16(sp)
+; RV32I-NEXT: sw a6, 20(sp)
+; RV32I-NEXT: call modfl
+; RV32I-NEXT: lw a0, 24(sp)
+; RV32I-NEXT: lw a1, 28(sp)
+; RV32I-NEXT: lw a2, 32(sp)
+; RV32I-NEXT: lw a3, 36(sp)
+; RV32I-NEXT: lw a4, 40(sp)
+; RV32I-NEXT: lw a5, 44(sp)
+; RV32I-NEXT: lw a6, 48(sp)
+; RV32I-NEXT: lw a7, 52(sp)
+; RV32I-NEXT: sw a4, 16(s0)
+; RV32I-NEXT: sw a5, 20(s0)
+; RV32I-NEXT: sw a6, 24(s0)
+; RV32I-NEXT: sw a7, 28(s0)
+; RV32I-NEXT: sw a0, 0(s0)
+; RV32I-NEXT: sw a1, 4(s0)
+; RV32I-NEXT: sw a2, 8(s0)
+; RV32I-NEXT: sw a3, 12(s0)
+; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .cfi_restore ra
+; RV32I-NEXT: .cfi_restore s0
+; RV32I-NEXT: addi sp, sp, 64
+; RV32I-NEXT: .cfi_def_cfa_offset 0
+; RV32I-NEXT: ret
+ %result = call { fp128, fp128 } @llvm.modf.f128(fp128 %a)
+ ret { fp128, fp128 } %result
+}
diff --git a/llvm/test/CodeGen/RISCV/half-intrinsics.ll b/llvm/test/CodeGen/RISCV/half-intrinsics.ll
index e16d788f66ede..379cc0878361e 100644
--- a/llvm/test/CodeGen/RISCV/half-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/half-intrinsics.ll
@@ -4417,3 +4417,205 @@ define half @tanh_f16(half %a) nounwind {
%1 = call half @llvm.tanh.f16(half %a)
ret half %1
}
+
+define { half, half } @test_modf_f16(half %a) {
+; RV32IZFH-LABEL: test_modf_f16:
+; RV32IZFH: # %bb.0:
+; RV32IZFH-NEXT: addi sp, sp, -16
+; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
+; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT: .cfi_offset ra, -4
+; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IZFH-NEXT: addi a0, sp, 8
+; RV32IZFH-NEXT: call modff
+; RV32IZFH-NEXT: flw fa5, 8(sp)
+; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFH-NEXT: fcvt.h.s fa1, fa5
+; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT: .cfi_restore ra
+; RV32IZFH-NEXT: addi sp, sp, 16
+; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFH-NEXT: ret
+;
+; RV64IZFH-LABEL: test_modf_f16:
+; RV64IZFH: # %bb.0:
+; RV64IZFH-NEXT: addi sp, sp, -16
+; RV64IZFH-NEXT: .cfi_def_cfa_offset 16
+; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFH-NEXT: .cfi_offset ra, -8
+; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV64IZFH-NEXT: addi a0, sp, 4
+; RV64IZFH-NEXT: call modff
+; RV64IZFH-NEXT: flw fa5, 4(sp)
+; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV64IZFH-NEXT: fcvt.h.s fa1, fa5
+; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFH-NEXT: .cfi_restore ra
+; RV64IZFH-NEXT: addi sp, sp, 16
+; RV64IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV64IZFH-NEXT: ret
+;
+; RV32IZHINX-LABEL: test_modf_f16:
+; RV32IZHINX: # %bb.0:
+; RV32IZHINX-NEXT: addi sp, sp, -16
+; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
+; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT: .cfi_offset ra, -4
+; RV32IZHINX-NEXT: fcvt.s.h a0, a0
+; RV32IZHINX-NEXT: addi a1, sp, 8
+; RV32IZHINX-NEXT: call modff
+; RV32IZHINX-NEXT: lw a1, 8(sp)
+; RV32IZHINX-NEXT: fcvt.h.s a0, a0
+; RV32IZHINX-NEXT: fcvt.h.s a1, a1
+; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT: .cfi_restore ra
+; RV32IZHINX-NEXT: addi sp, sp, 16
+; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINX-NEXT: ret
+;
+; RV64IZHINX-LABEL: test_modf_f16:
+; RV64IZHINX: # %bb.0:
+; RV64IZHINX-NEXT: addi sp, sp, -16
+; RV64IZHINX-NEXT: .cfi_def_cfa_offset 16
+; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT: .cfi_offset ra, -8
+; RV64IZHINX-NEXT: fcvt.s.h a0, a0
+; RV64IZHINX-NEXT: addi a1, sp, 4
+; RV64IZHINX-NEXT: call modff
+; RV64IZHINX-NEXT: lw a1, 4(sp)
+; RV64IZHINX-NEXT: fcvt.h.s a0, a0
+; RV64IZHINX-NEXT: fcvt.h.s a1, a1
+; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT: .cfi_restore ra
+; RV64IZHINX-NEXT: addi sp, sp, 16
+; RV64IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV64IZHINX-NEXT: ret
+;
+; RV32I-LABEL: test_modf_f16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: slli a0, a0, 16
+; RV32I-NEXT: srli a0, a0, 16
+; RV32I-NEXT: call __extendhfsf2
+; RV32I-NEXT: addi a1, sp, 4
+; RV32I-NEXT: call modff
+; RV32I-NEXT: call __truncsfhf2
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lw a0, 4(sp)
+; RV32I-NEXT: call __truncsfhf2
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .cfi_restore ra
+; RV32I-NEXT: .cfi_restore s0
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: .cfi_def_cfa_offset 0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_modf_f16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: .cfi_def_cfa_offset 32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: .cfi_offset s0, -16
+; RV64I-NEXT: slli a0, a0, 48
+; RV64I-NEXT: srli a0, a0, 48
+; RV64I-NEXT: call __extendhfsf2
+; RV64I-NEXT: addi a1, sp, 12
+; RV64I-NEXT: call modff
+; RV64I-NEXT: call __truncsfhf2
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lw a0, 12(sp)
+; RV64I-NEXT: call __truncsfhf2
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: .cfi_restore ra
+; RV64I-NEXT: .cfi_restore s0
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: .cfi_def_cfa_offset 0
+; RV64I-NEXT: ret
+;
+; RV32IZFHMIN-LABEL: test_modf_f16:
+; RV32IZFHMIN: # %bb.0:
+; RV32IZFHMIN-NEXT: addi sp, sp, -16
+; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
+; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
+; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT: addi a0, sp, 8
+; RV32IZFHMIN-NEXT: call modff
+; RV32IZFHMIN-NEXT: flw fa5, 8(sp)
+; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFHMIN-NEXT: fcvt.h.s fa1, fa5
+; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT: .cfi_restore ra
+; RV32IZFHMIN-NEXT: addi sp, sp, 16
+; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFHMIN-NEXT: ret
+;
+; RV64IZFHMIN-LABEL: test_modf_f16:
+; RV64IZFHMIN: # %bb.0:
+; RV64IZFHMIN-NEXT: addi sp, sp, -16
+; RV64IZFHMIN-NEXT: .cfi_def_cfa_offset 16
+; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT: .cfi_offset ra, -8
+; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
+; RV64IZFHMIN-NEXT: addi a0, sp, 4
+; RV64IZFHMIN-NEXT: call modff
+; RV64IZFHMIN-NEXT: flw fa5, 4(sp)
+; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
+; RV64IZFHMIN-NEXT: fcvt.h.s fa1, fa5
+; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT: .cfi_restore ra
+; RV64IZFHMIN-NEXT: addi sp, sp, 16
+; RV64IZFHMIN-NEXT: .cfi_def_cfa_offset 0
+; RV64IZFHMIN-NEXT: ret
+;
+; RV32IZHINXMIN-LABEL: test_modf_f16:
+; RV32IZHINXMIN: # %bb.0:
+; RV32IZHINXMIN-NEXT: addi sp, sp, -16
+; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
+; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: addi a1, sp, 8
+; RV32IZHINXMIN-NEXT: call modff
+; RV32IZHINXMIN-NEXT: lw a1, 8(sp)
+; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT: fcvt.h.s a1, a1
+; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT: .cfi_restore ra
+; RV32IZHINXMIN-NEXT: addi sp, sp, 16
+; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINXMIN-NEXT: ret
+;
+; RV64IZHINXMIN-LABEL: test_modf_f16:
+; RV64IZHINXMIN: # %bb.0:
+; RV64IZHINXMIN-NEXT: addi sp, sp, -16
+; RV64IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
+; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT: .cfi_offset ra, -8
+; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT: addi a1, sp, 4
+; RV64IZHINXMIN-NEXT: call modff
+; RV64IZHINXMIN-NEXT: lw a1, 4(sp)
+; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT: fcvt.h.s a1, a1
+; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-NEXT: .cfi_restore ra
+; RV64IZHINXMIN-NEXT: addi sp, sp, 16
+; RV64IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
+; RV64IZHINXMIN-NEXT: ret
+ %result = call { half, half } @llvm.modf.f16(half %a)
+ ret { half, half } %result
+}
>From 3e6cf277f893297e38ca88aea60b9995a2b342c2 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 2 Oct 2025 21:08:11 -0700
Subject: [PATCH 2/2] fixup! Add nounwind to tests
---
.../RISCV/GlobalISel/double-intrinsics.ll | 20 +-------
.../RISCV/GlobalISel/float-intrinsics.ll | 22 +--------
llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll | 8 +---
llvm/test/CodeGen/RISCV/double-intrinsics.ll | 28 +----------
llvm/test/CodeGen/RISCV/float-intrinsics.ll | 30 +-----------
llvm/test/CodeGen/RISCV/fp128.ll | 8 +---
llvm/test/CodeGen/RISCV/half-intrinsics.ll | 46 +------------------
7 files changed, 7 insertions(+), 155 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll b/llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
index f78bacb22973d..4b0acda839ad6 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
@@ -1421,45 +1421,34 @@ define double @tanh_f64(double %a) nounwind {
ret double %1
}
-define { double, double } @test_modf_f64(double %a) {
+define { double, double } @test_modf_f64(double %a) nounwind {
; RV32IFD-LABEL: test_modf_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
-; RV32IFD-NEXT: .cfi_def_cfa_offset 16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IFD-NEXT: .cfi_offset ra, -4
; RV32IFD-NEXT: mv a0, sp
; RV32IFD-NEXT: call modf
; RV32IFD-NEXT: fld fa1, 0(sp)
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IFD-NEXT: .cfi_restore ra
; RV32IFD-NEXT: addi sp, sp, 16
-; RV32IFD-NEXT: .cfi_def_cfa_offset 0
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_modf_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
-; RV64IFD-NEXT: .cfi_def_cfa_offset 16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IFD-NEXT: .cfi_offset ra, -8
; RV64IFD-NEXT: mv a0, sp
; RV64IFD-NEXT: call modf
; RV64IFD-NEXT: fld fa1, 0(sp)
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IFD-NEXT: .cfi_restore ra
; RV64IFD-NEXT: addi sp, sp, 16
-; RV64IFD-NEXT: .cfi_def_cfa_offset 0
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: test_modf_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: .cfi_offset ra, -4
-; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: mv a1, a2
@@ -1473,25 +1462,18 @@ define { double, double } @test_modf_f64(double %a) {
; RV32I-NEXT: sw a3, 12(s0)
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: .cfi_restore ra
-; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_modf_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: call modf
; RV64I-NEXT: ld a1, 0(sp)
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
%result = call { double, double } @llvm.modf.f64(double %a)
ret { double, double } %result
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
index 4b2758709fb84..01d9ceb0a0860 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
@@ -2119,80 +2119,60 @@ define float @tanh_f32(float %a) nounwind {
ret float %1
}
-define { float, float } @test_modf_f32(float %a) {
+define { float, float } @test_modf_f32(float %a) nounwind {
; RV32IF-LABEL: test_modf_f32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
-; RV32IF-NEXT: .cfi_def_cfa_offset 16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: addi a0, sp, 8
; RV32IF-NEXT: call modff
; RV32IF-NEXT: flw fa1, 8(sp)
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IF-NEXT: .cfi_restore ra
; RV32IF-NEXT: addi sp, sp, 16
-; RV32IF-NEXT: .cfi_def_cfa_offset 0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_modf_f32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16
-; RV64IF-NEXT: .cfi_def_cfa_offset 16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IF-NEXT: .cfi_offset ra, -8
; RV64IF-NEXT: addi a0, sp, 4
; RV64IF-NEXT: call modff
; RV64IF-NEXT: flw fa1, 4(sp)
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IF-NEXT: .cfi_restore ra
; RV64IF-NEXT: addi sp, sp, 16
-; RV64IF-NEXT: .cfi_def_cfa_offset 0
; RV64IF-NEXT: ret
;
; RV64IFD-LABEL: test_modf_f32:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
-; RV64IFD-NEXT: .cfi_def_cfa_offset 16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IFD-NEXT: .cfi_offset ra, -8
; RV64IFD-NEXT: addi a0, sp, 4
; RV64IFD-NEXT: call modff
; RV64IFD-NEXT: flw fa1, 4(sp)
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IFD-NEXT: .cfi_restore ra
; RV64IFD-NEXT: addi sp, sp, 16
-; RV64IFD-NEXT: .cfi_def_cfa_offset 0
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: test_modf_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: call modff
; RV32I-NEXT: lw a1, 8(sp)
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_modf_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: call modff
; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
%result = call { float, float } @llvm.modf.f32(float %a)
ret { float, float } %result
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll b/llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
index f3716c9f80cdd..e7a3f79acfad6 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
@@ -912,15 +912,12 @@ define fp128 @tanh(fp128 %a) nounwind {
ret fp128 %1
}
-define { fp128, fp128 } @modf(fp128 %a) {
+define { fp128, fp128 } @modf(fp128 %a) nounwind {
; CHECK-LABEL: modf:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -32
-; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; CHECK-NEXT: .cfi_offset ra, -8
-; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: mv a1, a2
@@ -934,10 +931,7 @@ define { fp128, fp128 } @modf(fp128 %a) {
; CHECK-NEXT: sd a3, 24(s0)
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; CHECK-NEXT: .cfi_restore ra
-; CHECK-NEXT: .cfi_restore s0
; CHECK-NEXT: addi sp, sp, 32
-; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
%result = call { fp128, fp128 } @llvm.modf.f128(fp128 %a)
ret { fp128, fp128 } %result
diff --git a/llvm/test/CodeGen/RISCV/double-intrinsics.ll b/llvm/test/CodeGen/RISCV/double-intrinsics.ll
index e1a9bf49b16e2..aaa08b577c4f4 100644
--- a/llvm/test/CodeGen/RISCV/double-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/double-intrinsics.ll
@@ -2110,76 +2110,57 @@ define double @tanh_f64(double %a) nounwind {
ret double %1
}
-define { double, double } @test_modf_f64(double %a) {
+define { double, double } @test_modf_f64(double %a) nounwind {
; RV32IFD-LABEL: test_modf_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
-; RV32IFD-NEXT: .cfi_def_cfa_offset 16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IFD-NEXT: .cfi_offset ra, -4
; RV32IFD-NEXT: mv a0, sp
; RV32IFD-NEXT: call modf
; RV32IFD-NEXT: fld fa1, 0(sp)
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IFD-NEXT: .cfi_restore ra
; RV32IFD-NEXT: addi sp, sp, 16
-; RV32IFD-NEXT: .cfi_def_cfa_offset 0
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_modf_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
-; RV64IFD-NEXT: .cfi_def_cfa_offset 16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IFD-NEXT: .cfi_offset ra, -8
; RV64IFD-NEXT: mv a0, sp
; RV64IFD-NEXT: call modf
; RV64IFD-NEXT: fld fa1, 0(sp)
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IFD-NEXT: .cfi_restore ra
; RV64IFD-NEXT: addi sp, sp, 16
-; RV64IFD-NEXT: .cfi_def_cfa_offset 0
; RV64IFD-NEXT: ret
;
; RV32IZFINXZDINX-LABEL: test_modf_f64:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
; RV32IZFINXZDINX-NEXT: mv a2, sp
; RV32IZFINXZDINX-NEXT: call modf
; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: .cfi_restore ra
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_modf_f64:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV64IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IZFINXZDINX-NEXT: .cfi_offset ra, -8
; RV64IZFINXZDINX-NEXT: mv a1, sp
; RV64IZFINXZDINX-NEXT: call modf
; RV64IZFINXZDINX-NEXT: ld a1, 0(sp)
; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IZFINXZDINX-NEXT: .cfi_restore ra
; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
-; RV64IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: test_modf_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: .cfi_offset ra, -4
-; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: mv a3, a2
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv a2, sp
@@ -2194,25 +2175,18 @@ define { double, double } @test_modf_f64(double %a) {
; RV32I-NEXT: sw a3, 12(s0)
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: .cfi_restore ra
-; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_modf_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: call modf
; RV64I-NEXT: ld a1, 0(sp)
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
%result = call { double, double } @llvm.modf.f64(double %a)
ret { double, double } %result
diff --git a/llvm/test/CodeGen/RISCV/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/float-intrinsics.ll
index bfeaa7d70aff2..5f673ac17d569 100644
--- a/llvm/test/CodeGen/RISCV/float-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/float-intrinsics.ll
@@ -3051,110 +3051,82 @@ define float @tanh_f32(float %a) nounwind {
ret float %1
}
-define { float, float } @test_modf_f32(float %a) {
+define { float, float } @test_modf_f32(float %a) nounwind {
; RV32IF-LABEL: test_modf_f32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
-; RV32IF-NEXT: .cfi_def_cfa_offset 16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: addi a0, sp, 8
; RV32IF-NEXT: call modff
; RV32IF-NEXT: flw fa1, 8(sp)
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IF-NEXT: .cfi_restore ra
; RV32IF-NEXT: addi sp, sp, 16
-; RV32IF-NEXT: .cfi_def_cfa_offset 0
; RV32IF-NEXT: ret
;
; RV32IZFINX-LABEL: test_modf_f32:
; RV32IZFINX: # %bb.0:
; RV32IZFINX-NEXT: addi sp, sp, -16
-; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFINX-NEXT: .cfi_offset ra, -4
; RV32IZFINX-NEXT: addi a1, sp, 8
; RV32IZFINX-NEXT: call modff
; RV32IZFINX-NEXT: lw a1, 8(sp)
; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFINX-NEXT: .cfi_restore ra
; RV32IZFINX-NEXT: addi sp, sp, 16
-; RV32IZFINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINX-NEXT: ret
;
; RV64IF-LABEL: test_modf_f32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16
-; RV64IF-NEXT: .cfi_def_cfa_offset 16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IF-NEXT: .cfi_offset ra, -8
; RV64IF-NEXT: addi a0, sp, 4
; RV64IF-NEXT: call modff
; RV64IF-NEXT: flw fa1, 4(sp)
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IF-NEXT: .cfi_restore ra
; RV64IF-NEXT: addi sp, sp, 16
-; RV64IF-NEXT: .cfi_def_cfa_offset 0
; RV64IF-NEXT: ret
;
; RV64IZFINX-LABEL: test_modf_f32:
; RV64IZFINX: # %bb.0:
; RV64IZFINX-NEXT: addi sp, sp, -16
-; RV64IZFINX-NEXT: .cfi_def_cfa_offset 16
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IZFINX-NEXT: .cfi_offset ra, -8
; RV64IZFINX-NEXT: addi a1, sp, 4
; RV64IZFINX-NEXT: call modff
; RV64IZFINX-NEXT: lw a1, 4(sp)
; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IZFINX-NEXT: .cfi_restore ra
; RV64IZFINX-NEXT: addi sp, sp, 16
-; RV64IZFINX-NEXT: .cfi_def_cfa_offset 0
; RV64IZFINX-NEXT: ret
;
; RV64IFD-LABEL: test_modf_f32:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
-; RV64IFD-NEXT: .cfi_def_cfa_offset 16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IFD-NEXT: .cfi_offset ra, -8
; RV64IFD-NEXT: addi a0, sp, 4
; RV64IFD-NEXT: call modff
; RV64IFD-NEXT: flw fa1, 4(sp)
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IFD-NEXT: .cfi_restore ra
; RV64IFD-NEXT: addi sp, sp, 16
-; RV64IFD-NEXT: .cfi_def_cfa_offset 0
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: test_modf_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: call modff
; RV32I-NEXT: lw a1, 8(sp)
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_modf_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: call modff
; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
%result = call { float, float } @llvm.modf.f32(float %a)
ret { float, float } %result
diff --git a/llvm/test/CodeGen/RISCV/fp128.ll b/llvm/test/CodeGen/RISCV/fp128.ll
index db03a9b0bf42d..704cb425c0eb4 100644
--- a/llvm/test/CodeGen/RISCV/fp128.ll
+++ b/llvm/test/CodeGen/RISCV/fp128.ll
@@ -190,15 +190,12 @@ define fp128 @fminimum(fp128 %x, fp128 %y) {
ret fp128 %a
}
-define { fp128, fp128 } @modf(fp128 %a) {
+define { fp128, fp128 } @modf(fp128 %a) nounwind {
; RV32I-LABEL: modf:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -64
-; RV32I-NEXT: .cfi_def_cfa_offset 64
; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
-; RV32I-NEXT: .cfi_offset ra, -4
-; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a4, 4(a1)
; RV32I-NEXT: lw a5, 8(a1)
@@ -230,10 +227,7 @@ define { fp128, fp128 } @modf(fp128 %a) {
; RV32I-NEXT: sw a3, 12(s0)
; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
-; RV32I-NEXT: .cfi_restore ra
-; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: addi sp, sp, 64
-; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
%result = call { fp128, fp128 } @llvm.modf.f128(fp128 %a)
ret { fp128, fp128 } %result
diff --git a/llvm/test/CodeGen/RISCV/half-intrinsics.ll b/llvm/test/CodeGen/RISCV/half-intrinsics.ll
index 379cc0878361e..847054d96968a 100644
--- a/llvm/test/CodeGen/RISCV/half-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/half-intrinsics.ll
@@ -4418,13 +4418,11 @@ define half @tanh_f16(half %a) nounwind {
ret half %1
}
-define { half, half } @test_modf_f16(half %a) {
+define { half, half } @test_modf_f16(half %a) nounwind {
; RV32IZFH-LABEL: test_modf_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: .cfi_offset ra, -4
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: addi a0, sp, 8
; RV32IZFH-NEXT: call modff
@@ -4432,17 +4430,13 @@ define { half, half } @test_modf_f16(half %a) {
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: fcvt.h.s fa1, fa5
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: .cfi_restore ra
; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_modf_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
-; RV64IZFH-NEXT: .cfi_def_cfa_offset 16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IZFH-NEXT: .cfi_offset ra, -8
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: addi a0, sp, 4
; RV64IZFH-NEXT: call modff
@@ -4450,17 +4444,13 @@ define { half, half } @test_modf_f16(half %a) {
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IZFH-NEXT: fcvt.h.s fa1, fa5
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IZFH-NEXT: .cfi_restore ra
; RV64IZFH-NEXT: addi sp, sp, 16
-; RV64IZFH-NEXT: .cfi_def_cfa_offset 0
; RV64IZFH-NEXT: ret
;
; RV32IZHINX-LABEL: test_modf_f16:
; RV32IZHINX: # %bb.0:
; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: .cfi_offset ra, -4
; RV32IZHINX-NEXT: fcvt.s.h a0, a0
; RV32IZHINX-NEXT: addi a1, sp, 8
; RV32IZHINX-NEXT: call modff
@@ -4468,17 +4458,13 @@ define { half, half } @test_modf_f16(half %a) {
; RV32IZHINX-NEXT: fcvt.h.s a0, a0
; RV32IZHINX-NEXT: fcvt.h.s a1, a1
; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: .cfi_restore ra
; RV32IZHINX-NEXT: addi sp, sp, 16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_modf_f16:
; RV64IZHINX: # %bb.0:
; RV64IZHINX-NEXT: addi sp, sp, -16
-; RV64IZHINX-NEXT: .cfi_def_cfa_offset 16
; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IZHINX-NEXT: .cfi_offset ra, -8
; RV64IZHINX-NEXT: fcvt.s.h a0, a0
; RV64IZHINX-NEXT: addi a1, sp, 4
; RV64IZHINX-NEXT: call modff
@@ -4486,19 +4472,14 @@ define { half, half } @test_modf_f16(half %a) {
; RV64IZHINX-NEXT: fcvt.h.s a0, a0
; RV64IZHINX-NEXT: fcvt.h.s a1, a1
; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IZHINX-NEXT: .cfi_restore ra
; RV64IZHINX-NEXT: addi sp, sp, 16
-; RV64IZHINX-NEXT: .cfi_def_cfa_offset 0
; RV64IZHINX-NEXT: ret
;
; RV32I-LABEL: test_modf_f16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: .cfi_offset ra, -4
-; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: call __extendhfsf2
@@ -4512,20 +4493,14 @@ define { half, half } @test_modf_f16(half %a) {
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: .cfi_restore ra
-; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_modf_f16:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
-; RV64I-NEXT: .cfi_def_cfa_offset 32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: .cfi_offset ra, -8
-; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: call __extendhfsf2
@@ -4539,18 +4514,13 @@ define { half, half } @test_modf_f16(half %a) {
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: .cfi_restore ra
-; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: addi sp, sp, 32
-; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; RV32IZFHMIN-LABEL: test_modf_f16:
; RV32IZFHMIN: # %bb.0:
; RV32IZFHMIN-NEXT: addi sp, sp, -16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
; RV32IZFHMIN-NEXT: addi a0, sp, 8
; RV32IZFHMIN-NEXT: call modff
@@ -4558,17 +4528,13 @@ define { half, half } @test_modf_f16(half %a) {
; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
; RV32IZFHMIN-NEXT: fcvt.h.s fa1, fa5
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFHMIN-NEXT: .cfi_restore ra
; RV32IZFHMIN-NEXT: addi sp, sp, 16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_modf_f16:
; RV64IZFHMIN: # %bb.0:
; RV64IZFHMIN-NEXT: addi sp, sp, -16
-; RV64IZFHMIN-NEXT: .cfi_def_cfa_offset 16
; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IZFHMIN-NEXT: .cfi_offset ra, -8
; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
; RV64IZFHMIN-NEXT: addi a0, sp, 4
; RV64IZFHMIN-NEXT: call modff
@@ -4576,17 +4542,13 @@ define { half, half } @test_modf_f16(half %a) {
; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
; RV64IZFHMIN-NEXT: fcvt.h.s fa1, fa5
; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IZFHMIN-NEXT: .cfi_restore ra
; RV64IZFHMIN-NEXT: addi sp, sp, 16
-; RV64IZFHMIN-NEXT: .cfi_def_cfa_offset 0
; RV64IZFHMIN-NEXT: ret
;
; RV32IZHINXMIN-LABEL: test_modf_f16:
; RV32IZHINXMIN: # %bb.0:
; RV32IZHINXMIN-NEXT: addi sp, sp, -16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
; RV32IZHINXMIN-NEXT: addi a1, sp, 8
; RV32IZHINXMIN-NEXT: call modff
@@ -4594,17 +4556,13 @@ define { half, half } @test_modf_f16(half %a) {
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: fcvt.h.s a1, a1
; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT: .cfi_restore ra
; RV32IZHINXMIN-NEXT: addi sp, sp, 16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_modf_f16:
; RV64IZHINXMIN: # %bb.0:
; RV64IZHINXMIN-NEXT: addi sp, sp, -16
-; RV64IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IZHINXMIN-NEXT: .cfi_offset ra, -8
; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
; RV64IZHINXMIN-NEXT: addi a1, sp, 4
; RV64IZHINXMIN-NEXT: call modff
@@ -4612,9 +4570,7 @@ define { half, half } @test_modf_f16(half %a) {
; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV64IZHINXMIN-NEXT: fcvt.h.s a1, a1
; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IZHINXMIN-NEXT: .cfi_restore ra
; RV64IZHINXMIN-NEXT: addi sp, sp, 16
-; RV64IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
; RV64IZHINXMIN-NEXT: ret
%result = call { half, half } @llvm.modf.f16(half %a)
ret { half, half } %result
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