[llvm] [RISCV][GISel] Use relaxed_load/store in GISel atomic patterns. NFC (PR #161712)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/161712

We have additional patterns for GISel because we need to make s16 and s32 legal for load/store. GISel does not distinquish integer and FP scalar types in LLT. We only know whether the load should be integer or FP after register bank selection.

These patterns should have been updated to use relaxed_load/store when the patterns in RISCVInstrInfoA.td were updated. Without this we will miscompile loads/stores with strong memory ordering when Zalasr is enabled.

This patch just fixes the miscompile, Zalasr will now cause a GISel abort in some cases. A follow up patch will add additional GISel patterns for Zalasr.

>From fb7d005105f78609b8c3d03ca59304312e47d66a Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 2 Oct 2025 10:58:51 -0700
Subject: [PATCH] [RISCV][GISel] Use relaxed_load/store in GISel atomic
 patterns. NFC

We have additional patterns for GISel because we need to make s16 and
s32 legal for load/store. GISel does not distinquish integer
and FP scalar types in LLT. We only know whether the load should
be integer or FP after register bank selection.

These patterns should have been updated to use relaxed_load/store
when the patterns in RISCVInstrInfoA.td were updated. Without this
we will miscompile loads/stores with strong memory ordering when
Zalasr is enabled.

This patch just fixes the miscompile, Zalasr will now cause a GISel
abort in some cases. A follow up patch will add additional GISel
patterns for Zalasr.
---
 llvm/lib/Target/RISCV/RISCVGISel.td | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index 19d5aff023d53..24579d4863dd8 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -110,16 +110,16 @@ def : StPat<truncstorei8, SB, GPR, i16>;
 
 let Predicates = [HasAtomicLdSt] in {
   // Prefer unsigned due to no c.lb in Zcb.
-  def : LdPat<atomic_load_aext_8,    LBU, i16>;
-  def : LdPat<atomic_load_nonext_16, LH,  i16>;
+  def : LdPat<relaxed_load<atomic_load_aext_8>,    LBU, i16>;
+  def : LdPat<relaxed_load<atomic_load_nonext_16>, LH,  i16>;
 
-  def : StPat<atomic_store_8,  SB, GPR, i16>;
-  def : StPat<atomic_store_16, SH, GPR, i16>;
+  def : StPat<relaxed_store<atomic_store_8>,  SB, GPR, i16>;
+  def : StPat<relaxed_store<atomic_store_16>, SH, GPR, i16>;
 }
 
 let Predicates = [HasAtomicLdSt, IsRV64] in {
-  def : LdPat<atomic_load_nonext_32, LW, i32>;
-  def : StPat<atomic_store_32, SW, GPR, i32>;
+  def : LdPat<relaxed_load<atomic_load_nonext_32>, LW, i32>;
+  def : StPat<relaxed_store<atomic_store_32>, SW, GPR, i32>;
 }
 
 //===----------------------------------------------------------------------===//