[llvm] [X86] Create special case for (a-b) - (a<b) -> sbb a, b (PR #161388)

via llvm-commits llvm-commits at lists.llvm.org
Thu Oct 2 07:01:51 PDT 2025


https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/161388

>From 25e179dcce6b9f5193652b02f194e1a240b18011 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Tue, 30 Sep 2025 10:20:41 -0400
Subject: [PATCH 1/2] Pre-commit test (NFC)

---
 llvm/test/CodeGen/X86/sbb.ll | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/llvm/test/CodeGen/X86/sbb.ll b/llvm/test/CodeGen/X86/sbb.ll
index 78d609d3a17e6..fe24e6616df9f 100644
--- a/llvm/test/CodeGen/X86/sbb.ll
+++ b/llvm/test/CodeGen/X86/sbb.ll
@@ -365,3 +365,36 @@ define i32 @uge_sext_add(i32 %0, i32 %1, i32 %2) {
   %6 = add nsw i32 %5, %0
   ret i32 %6
 }
+
+define i32 @sub_sub_ugt(i32 %a, i32 %b) {
+; CHECK-LABEL: sub_sub_ugt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    subl %esi, %eax
+; CHECK-NEXT:    seta %cl
+; CHECK-NEXT:    subl %ecx, %eax
+; CHECK-NEXT:    retq
+  %cmp = icmp ugt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  %sub = sub i32 %a, %b
+  %res = sub i32 %sub, %conv
+  ret i32 %res
+}
+
+define i32 @sub_sub_ult(i32 %a, i32 %b) {
+; CHECK-LABEL: sub_sub_ult:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    subl %esi, %eax
+; CHECK-NEXT:    seta %cl
+; CHECK-NEXT:    subl %ecx, %eax
+; CHECK-NEXT:    retq
+  %cmp = icmp ult i32 %b, %a
+  %conv = zext i1 %cmp to i32
+  %sub = sub i32 %a, %b
+  %res = sub i32 %sub, %conv
+  ret i32 %res
+}
+

>From 87c80aac76cc6fa5ae6f97886017cda066f7c9ac Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Tue, 30 Sep 2025 10:47:19 -0400
Subject: [PATCH 2/2] [X86] Create special case for (a-b) - (a< b) -> sbb a, b

---
 llvm/lib/Target/X86/X86ISelLowering.cpp | 46 ++++++++++++++++++++-----
 llvm/test/CodeGen/X86/sbb.ll            | 12 +++----
 2 files changed, 42 insertions(+), 16 deletions(-)

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 34854e4d8b6c0..cc2210f2455a5 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -52388,16 +52388,46 @@ static SDValue combineAddOrSubToADCOrSBB(bool IsSub, const SDLoc &DL, EVT VT,
     // Do not flip "e > c", where "c" is a constant, because Cmp instruction
     // cannot take an immediate as its first operand.
     //
-    if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.getNode()->hasOneUse() &&
+    // If EFLAGS is from a CMP that compares the same operands as the earlier
+    // SUB producing X (i.e. CMP X, Y), we can directly use the carry flag with
+    // SBB/ADC without creating a flipped SUB.
+    if (EFLAGS.getOpcode() == X86ISD::CMP &&
+        EFLAGS.getValueType().isInteger()) {
+      if (IsSub && X == EFLAGS.getOperand(0)) {
+        return DAG.getNode(X86ISD::SBB, DL, DAG.getVTList(VT, MVT::i32), X,
+                           DAG.getConstant(0, DL, VT), EFLAGS);
+      }
+      if (!IsSub && X == EFLAGS.getOperand(0)) {
+        return DAG.getNode(X86ISD::ADC, DL, DAG.getVTList(VT, MVT::i32), X,
+                           DAG.getConstant(0, DL, VT), EFLAGS);
+      }
+    }
+
+    if (EFLAGS.getOpcode() == X86ISD::SUB &&
         EFLAGS.getValueType().isInteger() &&
         !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
-      SDValue NewSub =
-          DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS), EFLAGS.getNode()->getVTList(),
-                      EFLAGS.getOperand(1), EFLAGS.getOperand(0));
-      SDValue NewEFLAGS = NewSub.getValue(EFLAGS.getResNo());
-      return DAG.getNode(IsSub ? X86ISD::SBB : X86ISD::ADC, DL,
-                         DAG.getVTList(VT, MVT::i32), X,
-                         DAG.getConstant(0, DL, VT), NewEFLAGS);
+      // Only create NewSub if we know one of the folds will succeed to avoid
+      // introducing a temporary node that may persist and affect one-use checks
+      // below.
+      if (EFLAGS.getNode()->hasOneUse()) {
+        SDValue NewSub = DAG.getNode(
+            X86ISD::SUB, SDLoc(EFLAGS), EFLAGS.getNode()->getVTList(),
+            EFLAGS.getOperand(1), EFLAGS.getOperand(0));
+        SDValue NewEFLAGS = NewSub.getValue(EFLAGS.getResNo());
+        return DAG.getNode(IsSub ? X86ISD::SBB : X86ISD::ADC, DL,
+                           DAG.getVTList(VT, MVT::i32), X,
+                           DAG.getConstant(0, DL, VT), NewEFLAGS);
+      }
+
+      if (IsSub && X == EFLAGS.getValue(0)) {
+        SDValue NewSub = DAG.getNode(
+            X86ISD::SUB, SDLoc(EFLAGS), EFLAGS.getNode()->getVTList(),
+            EFLAGS.getOperand(1), EFLAGS.getOperand(0));
+        SDValue NewEFLAGS = NewSub.getValue(EFLAGS.getResNo());
+        return DAG.getNode(X86ISD::SBB, DL, DAG.getVTList(VT, MVT::i32),
+                           EFLAGS.getOperand(0), EFLAGS.getOperand(1),
+                           NewEFLAGS);
+      }
     }
   }
 
diff --git a/llvm/test/CodeGen/X86/sbb.ll b/llvm/test/CodeGen/X86/sbb.ll
index fe24e6616df9f..f5a34688d67b5 100644
--- a/llvm/test/CodeGen/X86/sbb.ll
+++ b/llvm/test/CodeGen/X86/sbb.ll
@@ -370,10 +370,8 @@ define i32 @sub_sub_ugt(i32 %a, i32 %b) {
 ; CHECK-LABEL: sub_sub_ugt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    xorl %ecx, %ecx
-; CHECK-NEXT:    subl %esi, %eax
-; CHECK-NEXT:    seta %cl
-; CHECK-NEXT:    subl %ecx, %eax
+; CHECK-NEXT:    cmpl %edi, %esi
+; CHECK-NEXT:    sbbl %esi, %eax
 ; CHECK-NEXT:    retq
   %cmp = icmp ugt i32 %a, %b
   %conv = zext i1 %cmp to i32
@@ -386,10 +384,8 @@ define i32 @sub_sub_ult(i32 %a, i32 %b) {
 ; CHECK-LABEL: sub_sub_ult:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    xorl %ecx, %ecx
-; CHECK-NEXT:    subl %esi, %eax
-; CHECK-NEXT:    seta %cl
-; CHECK-NEXT:    subl %ecx, %eax
+; CHECK-NEXT:    cmpl %edi, %esi
+; CHECK-NEXT:    sbbl %esi, %eax
 ; CHECK-NEXT:    retq
   %cmp = icmp ult i32 %b, %a
   %conv = zext i1 %cmp to i32



More information about the llvm-commits mailing list