[llvm] [AMDGPU] Use fake16 load/store with +real-true16 and sram-ecc (PR #161256)

[Stanislav Mekhanoshin via llvm-commits]

rampitec wrote:

> > > ```
> > > 1. We can not simply use the16bit load/store fake16 pattern in true16 mode, since these has dst 16bit type but put it in a vgpr32 and isel will generate mismatched-size copy: `vgpr16 = COPY vgpr32`. We need to insert additional EXTRACT_SUBREG for these patterns in true16 mode. There is a draft patch(deprecated now) to address another D16 issue and its approach is similiar to this patch -- disabled D16 patterns for true16 mode. [[AMDGPU][True16][CodeGen] add a 16bit d16 predicate for true16 mode #156574](https://github.com/llvm/llvm-project/pull/156574) put it here for reference
> > > ```
> > 
> > 
> > Indeed. Interesting it does not trigger errors anywhere.
> 
> I think this does not trigger issue by itself, but confuses the following pass which use register class to do optimizations and cause functional error in the later flow. This usually hurts in the cts test.

Done

https://github.com/llvm/llvm-project/pull/161256