[llvm] fef7753 - [AArch64] Some tests for cbz/tbz with wzr. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 1 04:41:10 PDT 2025
Author: David Green
Date: 2025-10-01T12:41:03+01:00
New Revision: fef7753454a51f00d1300f30d1991696c00ba6f7
URL: https://github.com/llvm/llvm-project/commit/fef7753454a51f00d1300f30d1991696c00ba6f7
DIFF: https://github.com/llvm/llvm-project/commit/fef7753454a51f00d1300f30d1991696c00ba6f7.diff
LOG: [AArch64] Some tests for cbz/tbz with wzr. NFC
Added:
llvm/test/CodeGen/AArch64/cbz_wzr.mir
Modified:
llvm/test/CodeGen/AArch64/tbz-tbnz.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/cbz_wzr.mir b/llvm/test/CodeGen/AArch64/cbz_wzr.mir
new file mode 100644
index 0000000000000..7deea56ba23a1
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/cbz_wzr.mir
@@ -0,0 +1,260 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -o - %s -mtriple=aarch64-none-eabi -run-pass=machine-cp -mcp-use-is-copy-instr | FileCheck %s
+
+---
+name: cbz_wzr
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: cbz_wzr
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: CBZW $wzr, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $w0 = MOVZWi 10, 0
+ ; CHECK-NEXT: RET undef $lr, implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $w0 = MOVZWi 20, 0
+ ; CHECK-NEXT: RET undef $lr, implicit $w0
+ bb.0:
+ liveins: $x0
+
+ $w8 = ORRWrs $wzr, $wzr, 0
+ CBZW killed renamable $w8, %bb.2
+
+ bb.1:
+ $w0 = MOVZWi 10, 0
+ RET undef $lr, implicit $w0
+
+ bb.2:
+ $w0 = MOVZWi 20, 0
+ RET undef $lr, implicit $w0
+...
+---
+name: cbnz_wzr
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: cbnz_wzr
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: CBNZW $wzr, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $w0 = MOVZWi 10, 0
+ ; CHECK-NEXT: RET undef $lr, implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $w0 = MOVZWi 20, 0
+ ; CHECK-NEXT: RET undef $lr, implicit $w0
+ bb.0:
+ liveins: $x0
+
+ $w8 = ORRWrs $wzr, $wzr, 0
+ CBNZW killed renamable $w8, %bb.2
+
+ bb.1:
+ $w0 = MOVZWi 10, 0
+ RET undef $lr, implicit $w0
+
+ bb.2:
+ $w0 = MOVZWi 20, 0
+ RET undef $lr, implicit $w0
+...
+---
+name: tbz_wzr
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: tbz_wzr
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: TBZW $wzr, 0, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $w0 = MOVZWi 10, 0
+ ; CHECK-NEXT: RET undef $lr, implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $w0 = MOVZWi 20, 0
+ ; CHECK-NEXT: RET undef $lr, implicit $w0
+ bb.0:
+ liveins: $x0
+
+ $w8 = ORRWrs $wzr, $wzr, 0
+ TBZW killed renamable $w8, 0, %bb.2
+
+ bb.1:
+ $w0 = MOVZWi 10, 0
+ RET undef $lr, implicit $w0
+
+ bb.2:
+ $w0 = MOVZWi 20, 0
+ RET undef $lr, implicit $w0
+...
+---
+name: tbnz_wzr
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: tbnz_wzr
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: TBNZW $wzr, 0, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $w0 = MOVZWi 10, 0
+ ; CHECK-NEXT: RET undef $lr, implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $w0 = MOVZWi 20, 0
+ ; CHECK-NEXT: RET undef $lr, implicit $w0
+ bb.0:
+ liveins: $x0
+
+ $w8 = ORRWrs $wzr, $wzr, 0
+ TBNZW killed renamable $w8, 0, %bb.2
+
+ bb.1:
+ $w0 = MOVZWi 10, 0
+ RET undef $lr, implicit $w0
+
+ bb.2:
+ $w0 = MOVZWi 20, 0
+ RET undef $lr, implicit $w0
+...
+
+---
+name: cbz_xzr
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: cbz_xzr
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: CBZX $xzr, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $w0 = MOVZWi 10, 0
+ ; CHECK-NEXT: RET undef $lr, implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $w0 = MOVZWi 20, 0
+ ; CHECK-NEXT: RET undef $lr, implicit $w0
+ bb.0:
+ liveins: $x0
+
+ $x8 = ORRXrs $xzr, $xzr, 0
+ CBZX killed renamable $x8, %bb.2
+
+ bb.1:
+ $w0 = MOVZWi 10, 0
+ RET undef $lr, implicit $w0
+
+ bb.2:
+ $w0 = MOVZWi 20, 0
+ RET undef $lr, implicit $w0
+...
+---
+name: cbnz_xzr
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: cbnz_xzr
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: CBNZX $xzr, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $w0 = MOVZWi 10, 0
+ ; CHECK-NEXT: RET undef $lr, implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $w0 = MOVZWi 20, 0
+ ; CHECK-NEXT: RET undef $lr, implicit $w0
+ bb.0:
+ liveins: $x0
+
+ $x8 = ORRXrs $xzr, $xzr, 0
+ CBNZX killed renamable $x8, %bb.2
+
+ bb.1:
+ $w0 = MOVZWi 10, 0
+ RET undef $lr, implicit $w0
+
+ bb.2:
+ $w0 = MOVZWi 20, 0
+ RET undef $lr, implicit $w0
+...
+---
+name: tbz_xzr
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: tbz_xzr
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: TBZX $xzr, 0, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $w0 = MOVZWi 10, 0
+ ; CHECK-NEXT: RET undef $lr, implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $w0 = MOVZWi 20, 0
+ ; CHECK-NEXT: RET undef $lr, implicit $w0
+ bb.0:
+ liveins: $x0
+
+ $x8 = ORRXrs $xzr, $xzr, 0
+ TBZX killed renamable $x8, 0, %bb.2
+
+ bb.1:
+ $w0 = MOVZWi 10, 0
+ RET undef $lr, implicit $w0
+
+ bb.2:
+ $w0 = MOVZWi 20, 0
+ RET undef $lr, implicit $w0
+...
+---
+name: tbnz_xzr
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: tbnz_xzr
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: TBNZX $xzr, 0, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $w0 = MOVZWi 10, 0
+ ; CHECK-NEXT: RET undef $lr, implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $w0 = MOVZWi 20, 0
+ ; CHECK-NEXT: RET undef $lr, implicit $w0
+ bb.0:
+ liveins: $x0
+
+ $x8 = ORRXrs $xzr, $xzr, 0
+ TBNZX killed renamable $x8, 0, %bb.2
+
+ bb.1:
+ $w0 = MOVZWi 10, 0
+ RET undef $lr, implicit $w0
+
+ bb.2:
+ $w0 = MOVZWi 20, 0
+ RET undef $lr, implicit $w0
+...
diff --git a/llvm/test/CodeGen/AArch64/tbz-tbnz.ll b/llvm/test/CodeGen/AArch64/tbz-tbnz.ll
index 4a04934971711..6946cc23d867d 100644
--- a/llvm/test/CodeGen/AArch64/tbz-tbnz.ll
+++ b/llvm/test/CodeGen/AArch64/tbz-tbnz.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+; RUN: llc < %s -mtriple=aarch64 -O3 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 -O3 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
declare void @t()
@@ -581,3 +581,323 @@ end:
ret void
}
+define ptr @tbnz_wzr(i1 %cmp1.not.i, ptr %locflg) {
+; CHECK-SD-LABEL: tbnz_wzr:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB20_2
+; CHECK-SD-NEXT: // %bb.1:
+; CHECK-SD-NEXT: tbnz wzr, #0, .LBB20_3
+; CHECK-SD-NEXT: b .LBB20_4
+; CHECK-SD-NEXT: .LBB20_2: // %opnfil.exit.thread
+; CHECK-SD-NEXT: mov w8, #1 // =0x1
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: tbz w8, #0, .LBB20_4
+; CHECK-SD-NEXT: .LBB20_3: // %if.else25
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB20_4: // %common.ret
+; CHECK-SD-NEXT: mov x0, xzr
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tbnz_wzr:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov w8, #0 // =0x0
+; CHECK-GI-NEXT: tbz w0, #0, .LBB20_3
+; CHECK-GI-NEXT: // %bb.1: // %if.end10
+; CHECK-GI-NEXT: tbnz w8, #0, .LBB20_4
+; CHECK-GI-NEXT: .LBB20_2: // %common.ret
+; CHECK-GI-NEXT: mov x0, xzr
+; CHECK-GI-NEXT: ret
+; CHECK-GI-NEXT: .LBB20_3: // %opnfil.exit.thread
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: tbz w8, #0, .LBB20_2
+; CHECK-GI-NEXT: .LBB20_4: // %if.else25
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: mov x0, xzr
+; CHECK-GI-NEXT: ret
+entry:
+ br i1 %cmp1.not.i, label %if.end10, label %opnfil.exit.thread
+
+opnfil.exit.thread: ; preds = %entry
+ store i32 0, ptr %locflg, align 4
+ br label %if.end10
+
+if.end10: ; preds = %opnfil.exit.thread, %entry
+ %cmp5 = phi i1 [ true, %opnfil.exit.thread ], [ false, %entry ]
+ br i1 %cmp5, label %if.else25, label %if.then12
+
+if.then12: ; preds = %if.end10
+ %call20 = load i32, ptr null, align 4
+ br label %if.end26
+
+if.else25: ; preds = %if.end10
+ store i32 0, ptr %locflg, align 4
+ br label %if.end26
+
+if.end26: ; preds = %if.else25, %if.then12
+ br i1 %cmp5, label %common.ret, label %if.then28
+
+common.ret: ; preds = %if.then28, %if.end26
+ %common.ret.op = phi ptr [ null, %if.then28 ], [ null, %if.end26 ]
+ ret ptr %common.ret.op
+
+if.then28: ; preds = %if.end26
+ %0 = load ptr, ptr null, align 8
+ br label %common.ret
+}
+
+define ptr @tbz_wzr(i1 %cmp1.not.i, ptr %locflg) {
+; CHECK-SD-LABEL: tbz_wzr:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB21_2
+; CHECK-SD-NEXT: // %bb.1:
+; CHECK-SD-NEXT: mov w8, #1 // =0x1
+; CHECK-SD-NEXT: tbnz w8, #0, .LBB21_3
+; CHECK-SD-NEXT: b .LBB21_4
+; CHECK-SD-NEXT: .LBB21_2: // %opnfil.exit.thread
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: tbz wzr, #0, .LBB21_4
+; CHECK-SD-NEXT: .LBB21_3: // %if.else25
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB21_4: // %common.ret
+; CHECK-SD-NEXT: mov x0, xzr
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tbz_wzr:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: tbz w0, #0, .LBB21_3
+; CHECK-GI-NEXT: // %bb.1: // %if.end10
+; CHECK-GI-NEXT: tbnz w8, #0, .LBB21_4
+; CHECK-GI-NEXT: .LBB21_2: // %common.ret
+; CHECK-GI-NEXT: mov x0, xzr
+; CHECK-GI-NEXT: ret
+; CHECK-GI-NEXT: .LBB21_3: // %opnfil.exit.thread
+; CHECK-GI-NEXT: mov w8, #0 // =0x0
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: tbz w8, #0, .LBB21_2
+; CHECK-GI-NEXT: .LBB21_4: // %if.else25
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: mov x0, xzr
+; CHECK-GI-NEXT: ret
+entry:
+ br i1 %cmp1.not.i, label %if.end10, label %opnfil.exit.thread
+
+opnfil.exit.thread: ; preds = %entry
+ store i32 0, ptr %locflg, align 4
+ br label %if.end10
+
+if.end10: ; preds = %opnfil.exit.thread, %entry
+ %cmp5 = phi i1 [ false, %opnfil.exit.thread ], [ true, %entry ]
+ br i1 %cmp5, label %if.else25, label %if.then12
+
+if.then12: ; preds = %if.end10
+ %call20 = load i32, ptr null, align 4
+ br label %if.end26
+
+if.else25: ; preds = %if.end10
+ store i32 0, ptr %locflg, align 4
+ br label %if.end26
+
+if.end26: ; preds = %if.else25, %if.then12
+ br i1 %cmp5, label %common.ret, label %if.then28
+
+common.ret: ; preds = %if.then28, %if.end26
+ %common.ret.op = phi ptr [ null, %if.then28 ], [ null, %if.end26 ]
+ ret ptr %common.ret.op
+
+if.then28: ; preds = %if.end26
+ %0 = load ptr, ptr null, align 8
+ br label %common.ret
+}
+
+define ptr @cbnz_wzr(i1 %cmp1.not.i, ptr %locflg) {
+; CHECK-SD-LABEL: cbnz_wzr:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB22_2
+; CHECK-SD-NEXT: // %bb.1:
+; CHECK-SD-NEXT: cbnz wzr, .LBB22_3
+; CHECK-SD-NEXT: b .LBB22_4
+; CHECK-SD-NEXT: .LBB22_2: // %opnfil.exit.thread
+; CHECK-SD-NEXT: mov w8, #10 // =0xa
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: cbz w8, .LBB22_4
+; CHECK-SD-NEXT: .LBB22_3: // %if.else25
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB22_4: // %common.ret
+; CHECK-SD-NEXT: mov x0, xzr
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: cbnz_wzr:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov w8, wzr
+; CHECK-GI-NEXT: tbnz w0, #0, .LBB22_2
+; CHECK-GI-NEXT: // %bb.1: // %opnfil.exit.thread
+; CHECK-GI-NEXT: mov w8, #10 // =0xa
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB22_2: // %if.end10
+; CHECK-GI-NEXT: cbz w8, .LBB22_4
+; CHECK-GI-NEXT: // %bb.3: // %if.else25
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB22_4: // %common.ret
+; CHECK-GI-NEXT: mov x0, xzr
+; CHECK-GI-NEXT: ret
+entry:
+ br i1 %cmp1.not.i, label %if.end10, label %opnfil.exit.thread
+
+opnfil.exit.thread: ; preds = %entry
+ store i32 0, ptr %locflg, align 4
+ br label %if.end10
+
+if.end10: ; preds = %opnfil.exit.thread, %entry
+ %cmp5 = phi i32 [ 10, %opnfil.exit.thread ], [ 0, %entry ]
+ %cmp5b = icmp ne i32 %cmp5, 0
+ br i1 %cmp5b, label %if.else25, label %if.then12
+
+if.then12: ; preds = %if.end10
+ %call20 = load i32, ptr null, align 4
+ br label %if.end26
+
+if.else25: ; preds = %if.end10
+ store i32 0, ptr %locflg, align 4
+ br label %if.end26
+
+if.end26: ; preds = %if.else25, %if.then12
+ br i1 %cmp5b, label %common.ret, label %if.then28
+
+common.ret: ; preds = %if.then28, %if.end26
+ %common.ret.op = phi ptr [ null, %if.then28 ], [ null, %if.end26 ]
+ ret ptr %common.ret.op
+
+if.then28: ; preds = %if.end26
+ %0 = load ptr, ptr null, align 8
+ br label %common.ret
+}
+
+define ptr @cbz_wzr(i1 %cmp1.not.i, ptr %locflg) {
+; CHECK-SD-LABEL: cbz_wzr:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB23_2
+; CHECK-SD-NEXT: // %bb.1:
+; CHECK-SD-NEXT: mov w8, #10 // =0xa
+; CHECK-SD-NEXT: cbnz w8, .LBB23_3
+; CHECK-SD-NEXT: b .LBB23_4
+; CHECK-SD-NEXT: .LBB23_2: // %opnfil.exit.thread
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: cbz wzr, .LBB23_4
+; CHECK-SD-NEXT: .LBB23_3: // %if.else25
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB23_4: // %common.ret
+; CHECK-SD-NEXT: mov x0, xzr
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: cbz_wzr:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov w8, #10 // =0xa
+; CHECK-GI-NEXT: tbnz w0, #0, .LBB23_2
+; CHECK-GI-NEXT: // %bb.1: // %opnfil.exit.thread
+; CHECK-GI-NEXT: mov w8, wzr
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB23_2: // %if.end10
+; CHECK-GI-NEXT: cbz w8, .LBB23_4
+; CHECK-GI-NEXT: // %bb.3: // %if.else25
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB23_4: // %common.ret
+; CHECK-GI-NEXT: mov x0, xzr
+; CHECK-GI-NEXT: ret
+entry:
+ br i1 %cmp1.not.i, label %if.end10, label %opnfil.exit.thread
+
+opnfil.exit.thread: ; preds = %entry
+ store i32 0, ptr %locflg, align 4
+ br label %if.end10
+
+if.end10: ; preds = %opnfil.exit.thread, %entry
+ %cmp5 = phi i32 [ 0, %opnfil.exit.thread ], [ 10, %entry ]
+ %cmp5b = icmp ne i32 %cmp5, 0
+ br i1 %cmp5b, label %if.else25, label %if.then12
+
+if.then12: ; preds = %if.end10
+ %call20 = load i32, ptr null, align 4
+ br label %if.end26
+
+if.else25: ; preds = %if.end10
+ store i32 0, ptr %locflg, align 4
+ br label %if.end26
+
+if.end26: ; preds = %if.else25, %if.then12
+ br i1 %cmp5b, label %common.ret, label %if.then28
+
+common.ret: ; preds = %if.then28, %if.end26
+ %common.ret.op = phi ptr [ null, %if.then28 ], [ null, %if.end26 ]
+ ret ptr %common.ret.op
+
+if.then28: ; preds = %if.end26
+ %0 = load ptr, ptr null, align 8
+ br label %common.ret
+}
+
+define i1 @avifSequenceHeaderParse() {
+; CHECK-SD-LABEL: avifSequenceHeaderParse:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mov w8, #1 // =0x1
+; CHECK-SD-NEXT: cbz w8, .LBB24_2
+; CHECK-SD-NEXT: .LBB24_1: // %bb6
+; CHECK-SD-NEXT: mov w0, wzr
+; CHECK-SD-NEXT: ret
+; CHECK-SD-NEXT: .LBB24_2: // %bb1
+; CHECK-SD-NEXT: cbz w8, .LBB24_4
+; CHECK-SD-NEXT: // %bb.3:
+; CHECK-SD-NEXT: tbz xzr, #63, .LBB24_1
+; CHECK-SD-NEXT: b .LBB24_5
+; CHECK-SD-NEXT: .LBB24_4: // %bb2
+; CHECK-SD-NEXT: mov w8, #1 // =0x1
+; CHECK-SD-NEXT: tbz x8, #63, .LBB24_1
+; CHECK-SD-NEXT: .LBB24_5: // %bb4
+; CHECK-SD-NEXT: mov w8, #1 // =0x1
+; CHECK-SD-NEXT: mov w0, wzr
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: avifSequenceHeaderParse:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov w0, wzr
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: ret
+entry:
+ %a = icmp slt i64 0, 0
+ br i1 %a, label %bb1, label %bb6
+
+bb1: ; preds = %entry
+ %b = icmp eq i32 1, 0
+ br i1 %b, label %bb2, label %bb3
+
+bb2: ; preds = %bb1
+ %c = load i8, ptr null, align 1
+ %d = zext i8 1 to i64
+ %e = shl i64 %d, 0
+ br label %bb3
+
+bb3: ; preds = %bb2, %bb1
+ %f = phi i64 [ %e, %bb2 ], [ 0, %bb1 ]
+ %g = icmp slt i64 %f, 0
+ br i1 %g, label %bb4, label %bb6
+
+bb4: ; preds = %bb3
+ %h = icmp eq i32 1, 0
+ br i1 %h, label %bb5, label %bb7
+
+bb5: ; preds = %bb4
+ %i = load i8, ptr null, align 1
+ %j = shl i64 0, 0
+ br label %bb7
+
+bb6: ; preds = %bb7, %bb3, %entry
+ %k = phi i1 [ false, %bb7 ], [ false, %bb3 ], [ false, %entry ]
+ ret i1 %k
+
+bb7: ; preds = %bb5, %bb4
+ %l = phi ptr [ inttoptr (i64 1 to ptr), %bb5 ], [ null, %bb4 ]
+ %m = phi i64 [ %j, %bb5 ], [ 0, %bb4 ]
+ %n = icmp ult ptr %l, null
+ br label %bb6
+}
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