[llvm] [AMDGPU] Fix code sequence for barrier start in GFX10+ CU Mode (PR #160501)

[Sameer Sahasrabuddhe via llvm-commits]

ssahasra wrote:

Being safe sounds good to me. I honestly haven't thought about various combinations of a store that precedes an atomic store-release operation. In particular what is the hardware memory model implied by the programming guide for different counters. 

https://github.com/llvm/llvm-project/pull/160501