[llvm] [AMDGPU][GlobalISel] Add register bank legalization for G_SMIN/G_SMAX/G_UMIN/G_UMAX (PR #159821)

[Petar Avramovic via llvm-commits]

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@@ -1329,7 +1363,13 @@ void RegBankLegalizeHelper::applyMappingTrivial(MachineInstr &MI) {
     B.setInstr(MI);
     for (unsigned i = NumDefs; i < NumOperands; ++i) {
       Register Reg = MI.getOperand(i).getReg();
-      if (MRI.getRegBank(Reg) != RB) {
+      // Helper to check if a register should be skipped for VGPR conversion
+      auto shouldSkipVGPRConversion = [&](Register Reg) {
+        MachineInstr *DefMI = MRI.getVRegDef(Reg);
+        // Skip if defining instruction is implicit_def
+        return DefMI && DefMI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF;
+      };
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petar-avramovic wrote:

I really think this is not right approach. Assuming no combine or pattern optimizes away MI, operand in question would end up with vgpr register class and copy from sgpr_reg_class to vgpr_reg_class would have to be inserted.
Instead should teach pattern to look through copy, but since that creates other problems I would propose to leave fixme comment in lit test with regression and fix it later.

https://github.com/llvm/llvm-project/pull/159821