[llvm] [RISCV] Add commutative support for Qualcomm uC Xqcics extension (PR #161328)

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git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 3312d306a..1e6b04f8a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -4027,8 +4027,7 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
   case RISCV::QC_SELECTINE:
   case RISCV::QC_SELECTIIEQ:
   case RISCV::QC_SELECTIINE:
-    return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1,
-                                                   OpIdx2);
+    return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
   case RISCV::QC_MVEQ:
   case RISCV::QC_MVNE:
   case RISCV::QC_MVLT:

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https://github.com/llvm/llvm-project/pull/161328